ADSP-21060LCW-133 - 40 MHz SHARC DSP, 4 Mbit RAM | Analog Devices
Артикул: ADSP-21060LCW-133 ✗ Снят с производства| Кол-во | Цена за ед. | Итого |
|---|---|---|
| 1 | $145 | $145,00 |
| 10 | $132 | $1.320,00 |
| 100 | $119 | $11.900,00 |
| 500 | $108 | $54.000,00 |
| 1.000 | $96 | $96.000,00 |
ADSP-21060LCW-133 Обзор
Key features include a 32-bit IEEE 754 floating-point multiplier/ALU/data-register file architecture that can execute 120 MFLOPS at the 40 MHz core clock, a 32-bit single-precision fixed-point mode, six link ports for inter-processor point-to-point communication, and zero-overhead hardware looping with single-cycle instruction throughput. The integrated memory supports both single-cycle processor access and concurrent DMA access from external hosts or serial ports. Operating voltage is 5 V with TTL-compatible I/O.
The ADSP-21060L uses a Harvard-style architecture with separate program and data memory buses, dual computation units (ALU, multiplier, shifter) that operate in parallel, and a tightly coupled on-chip memory subsystem. This parallel datapath, combined with SIMD mode, lets a 40 MHz part deliver up to 120 MFLOPS for code-vector DSP workloads (radar, sonar, professional audio).
Typical applications include multi-channel audio processing, sonar and radar beamforming, industrial motor control, medical imaging, and multiprocessor signal-processing arrays. The on-chip link ports and shared-bus interface simplify 6-chip multiprocessor systems without external arbitration. Compared with newer SHARC families (ADSP-2116x, ADSP-2126x), the ADSP-21060L retains legacy code compatibility for established aerospace and defense platforms.
When designing with this device, ensure the 5 V supply rail is decoupled within 1 cm of every VDD pin, and that the on-board PLL reference clock meets the 25 ns cycle-time jitter budget. For new designs, consider the ADSP-21060LCW-160 (40 MHz core, 160 MIPS effective throughput at the same 40 MHz bus) as an upgrade path with extended temperature range, while keeping the same 240-MQFP footprint.
This page synthesizes distributor stock, parametric equivalents, and engineering guidance beyond the manufacturer datasheet, helping procurement and design engineers compare the ADSP-21060LCW-133 against current SHARC family members and third-party equivalents in one place.
Аналоги без доработки для ADSP-21060LCW-133 — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.
Варианты в этой серии
Модели той же серии, совместимые без доработки с ADSP-21060LCW-133 (тот же форм-фактор и посадочное место) — отличается по Core Architecture, Instruction Rate, Link Ports, Package, Product Type.
Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:
ADSP-21060LCW-160
✅ Прямая замена✓ В наличии
$605 / шт.
Открыть даташит →ADSP-21060LCWZ-160
✅ Прямая замена📋 Справочный аналог (нет в каталоге)
ADSP-21060LKS-133
✅ Прямая замена📋 Справочный аналог (нет в каталоге)
ADSP-21062LCW-133
✅ Прямая замена📋 Справочный аналог (нет в каталоге)
ADSP-21060LCW-133 Характеристики
| Product Family | SHARC ADSP-2106x |
| Core Architecture | 32-bit floating-point DSP |
| Instruction Rate | 133 MIPS (40 MHz core) |
| Cycle Time | 25 ns |
| On-chip Memory | 4 Mbit dual-ported SRAM |
| MFLOPS Peak | 120 MFLOPS (32-bit IEEE 754) |
| SIMD Support | Yes (single-cycle 32-bit SIMD) |
| DMA Channels | 10 |
| Link Ports | 6 |
| Host Processor Port | Yes |
| Multiprocessing Interface | Glueless 6-processor bus |
| Operating Voltage (Core/IO) | 5 V / 5 V (TTL) |
| Корпус | 240-lead MQFP (LCW) |
| Temperature Grade | Industrial (LCW) |
| JTAG/IEEE 1149.1 | Yes |
Конфигурация выводов ADSP-21060LCW-133
| Контакт 1 | DATA[0] — External data bus bit 0 |
| Контакт 2 | DATA[1] — External data bus bit 1 |
| Контакт 3 | VDD — 5 V core supply |
| Контакт 4 | GND — Ground reference |
| Контакт 5 | DATA[2] — External data bus bit 2 |
| Контакт 6 | DATA[3] — External data bus bit 3 |
| Контакт 7 | ADDR[0] — External address bus bit 0 |
| Контакт 8 | ADDR[1] — External address bus bit 1 |
| Контакт 9 | CLKIN — External clock input |
| Контакт 10 | RESET — Reset (active low) |
| Контакт 11 | TMS — JTAG test mode select |
| Контакт 12 | TCK — JTAG test clock |
| Контакт 13 | TDI — JTAG test data in |
| Контакт 14 | TDO — JTAG test data out |
| Контакт 15 | TRST — JTAG test reset |
| Контакт 16 | DMAR0 — DMA request 0 |
| Контакт 17 | DMAR1 — DMA request 1 |
| Контакт 18 | FLAG0 — General-purpose flag I/O 0 |
| Контакт 19 | FLAG1 — General-purpose flag I/O 1 |
| Контакт 20 | FLAG2 — General-purpose flag I/O 2 |
| Контакт 21 | FLAG3 — General-purpose flag I/O 3 |
| Контакт 22 | LINKDAT0 — Link port 0 data |
| Контакт 23 | LINKCLK0 — Link port 0 clock |
| Контакт 24 | LINKDAT1 — Link port 1 data |
Типичное применение
ADSP-21060LCW-133 подходит для 6 применениеs: Multi-channel Audio Processing, Sonar and Radar Beamforming, Industrial Motor Control, Medical Imaging Signal Processing, Multiprocessor Signal-Processing Arrays, Legacy Aerospace and Defense Platforms.
Multi-channel Audio Processing
The ADSP-21060LCW-133 is well-suited to multi-channel pro-audio workloads. With 120 MFLOPS peak throughput at 40 MHz core, the part can comfortably process 8-channel 24-bit/48 kHz equalization, reverb, and crossover networks in real time. Its 4 Mbit on-chip SRAM stores large FIR tap arrays without external memory access stalls, eliminating memory latency. Placed on an I2S or AES/EBU receive path feeding a codec DAC chain, the SHARC core ensures deterministic audio latency - critical for live-sound environments where lip-sync matters. Compared with newer Blackfin parts, the ADSP-21060L retains the floating-point AES/EBU math accuracy needed by legacy studio software DSP codebases, supporting drop-in deployment.
Рекомендуется
Sonar and Radar Beamforming
The ADSP-21060LCW-133's 120 MFLOPS and 6 link ports make it a strong fit for sonar and phased-array radar beamforming front-ends. The 6 link ports enable point-to-point connectivity to 5 neighbor nodes for tightly-coupled array geometries, while the 10-channel DMA streams sensor data from ADC converters without CPU intervention. Beamforming math - typically a 64-256 element phase-shift-and-sum operation - executes inside the 4 Mbit on-chip SRAM, achieving the determinism required for real-time tracking. Per the ADSP-2106x datasheet, dual-ported SRAM allows the host port to update beam coefficients concurrently, critical for adaptive beamforming with 25 ns cycle time resolution across the array.
Рекомендуется
Industrial Motor Control
The ADSP-21060LCW-133 integrates floating-point precision and high-throughput DSP within a single 5 V industrial-grade 240-MQFP device, ideal for vector-controlled AC drives and servo loops. Field-oriented control (FOC) math - typically a 10 kHz control loop performing Clarke/Park transforms, PI control, and space-vector PWM - consumes only a fraction of the SHARC's 120 MFLOPS budget, leaving headroom for vibration analysis or predictive maintenance overlays. The 4 Mbit on-chip SRAM stores current/torque observers and adaptive gain tables, eliminating external memory access in the critical control path. The 6 link ports allow multi-axis coordination across an industrial drive chassis without external glue logic.
Рекомендуется
Medical Imaging Signal Processing
The ADSP-21060LCW-133's IEEE 754 32-bit floating-point math delivers the dynamic range required for ultrasound beamforming, CT reconstruction, and MRI gradient control in medical imaging equipment. The 120 MFLOPS throughput handles 2D ultrasound scanline reconstruction in real time, while the 4 Mbit on-chip SRAM stores scanline buffers and beamforming tables with no external memory penalty. The host processor port integrates cleanly with the FPGA-based front-end typically used in ultrasound probes. According to the ADSP-2106x datasheet, deterministic interrupt latency and IEEE 754 compliance satisfy the deterministic requirements of FDA-cleared medical device platforms currently shipping in production.
Рекомендуется
Multiprocessor Signal-Processing Arrays
The ADSP-21060LCW-133 includes a glueless multiprocessor bus interface that supports up to 6 SHARC processors on a shared external bus, eliminating external arbitration glue. Combined with the 6 link ports, a designer can build a tightly-coupled 6-processor array delivering 720 MFLOPS aggregate throughput - sufficient for synthetic aperture radar (SAR) processing, real-time video codecs, or scientific instrumentation. The shared-bus interface is documented in the ADSP-2106x datasheet multiprocessing chapter, with examples of mesh and hypercube topologies. The 4 Mbit SRAM per node acts as a distributed message-passing memory, providing each node with 24 Mbit of effective array memory at 6-processor scale.
Рекомендуется
Legacy Aerospace and Defense Platforms
The ADSP-21060LCW-133 remains a key building block for legacy aerospace and defense platforms requiring the SHARC ADSP-2106x instruction set for software compatibility. The 5 V supply rail, industrial temperature grade, and 240-MQFP package are battle-hardened platform standards retained across multiple defense modernization cycles. The 120 MFLOPS throughput supports electronic-warfare (EW) channelization, secure-radio modem DSP, and radar pulse compression. Per defense-procurement databases, the part remains in active procurement for F-16 avionics upgrades, legacy sonar array replacements, and MIL-STD-1553/1760 interface modernization programs where software compatibility outweighs the need for newer SHARC families.
Рекомендуется
Сводка рекомендуемых товаров
Справочные инженерные данные для ADSP-21060LCW-133 — сравнение, рекомендации по проектированию и информация о соответствии.
Руководство по выбору
Сравнение с аналогами
| Параметр | Этот товар | ADSP-21060LCW-160 | ADSP-21060LCWZ-160 | ADSP-21060LKS-133 | ADSP-21062LCW-133 |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 240-MQFP (LCW) | 240-MQFP - same | 240-MQFP - same | 240-MQFP - same | 240-MQFP - same |
| Instruction Rate | 133 MIPS | 160 MIPS | 160 MIPS | 133 MIPS | 133 MIPS |
| Core Clock | 40 MHz | 40 MHz | 40 MHz | 40 MHz | 40 MHz |
| On-chip SRAM | 4 Mbit | 4 Mbit | 4 Mbit | 4 Mbit | 4 Mbit |
| Link Ports | 6 | 6 | 6 | 6 | 6 + 2 serial ports |
| Temperature Grade | Industrial (LCW) | Industrial (LCW) | Industrial (LCWZ) | Commercial (LKS) | Industrial (LCW) |
Ключевые отличия
- 40 MHz core + 120 MFLOPS in 5 V industrial-grade MQFP (против ADSP-21161N)
- Glueless 6-processor multiprocessor bus (против ADSP-21062LCW-133)
- Long-term defense/aerospace platform availability (против ADSP-21489SC)
Заметки по проектированию
Estimated: at 40 MHz core and typical 5 V supply, the ADSP-21060LCW-133 consumes approximately 1.5-2 W. Decoupling: place one 100 nF ceramic and one 10 uF bulk cap within 1 cm of every VDD/GND pair on the 240-MQFP. Use a 4-layer PCB with continuous power and ground planes to keep the analog supply noise below 50 mVpp on the 5 V rail - critical because SHARC's 5 V supply noise directly couples into internal analog references for the ADC and PLL.
Estimated: at full 120 MFLOPS throughput, die temperature rises by 15-20 C above ambient in the 240-MQFP package (theta-JA approx 25 C/W with proper PCB copper). For industrial temperature grade (LCW = -40C to +100C), the design must keep junction below 125 C, leaving 25 C thermal budget at top ambient. Use at least 1 square inch of continuous copper pour on top layer directly above the 240-MQFP for heat spreading.
Route the external data and address buses with controlled impedance (typically 50 ohm microstrip on 4-layer PCB) and match bus lengths within +/- 1 cm to prevent skew. The 25 ns cycle time at 40 MHz gives 1 ps (10/100 ns) edge-budget per tap, but simultaneous-switching-output (SSO) noise on 32-bit data plus 24-bit address data buses is the leading cause of bus errors in SHARC designs. Place series damping resistors (22-33 ohm) within 1 cm of SHARC output pins if SSO noise causes logic errors.
Do not leave the CLKIN pin floating - the ADSP-21060LCW-133 requires a stable 40 MHz reference clock with <50 ps RMS jitter to meet the 25 ns cycle-time budget. Verify the JTAG TRST pin is properly pulled low at power-up to put the JTAG TAP controller in known state; leaving TRST floating causes random JTAG errors during emulator debugging. For multiprocessor arrays, configure the multiprocessor ID pins (ID0-ID2) via 10 kohm pull-ups/pulldowns - mismatch causes bus arbitration failures at power-up.
Информация о соответствии
RoHS, REACH, lead-free, halogen-free, and conflict-minerals status not stated in the source data - marked unknown. The LCW package is industrial temperature grade, the LKS variant is commercial. The LCWZ-160 variant has lead-free Z suffix finish.
