EP2S90F780C4 - Stratix II FPGA, 90K LEs, 780-FBGA | Intel / Altera
Артикул: EP2S90F780C4 ✗ Снят с производства| Кол-во | Цена за ед. | Итого |
|---|---|---|
| 1 | $4050.99 | $4.050,99 |
| 10 | $3800 | $38.000,00 |
| 50 | $3550 | $177.500,00 |
| 100 | $3300 | $330.000,00 |
| 500 | $3050 | $1.525.000,00 |
EP2S90F780C4 Обзор
A Field-Programmable Gate Array (FPGA) is a type of programmable logic device (PLD) that allows engineers to implement custom digital circuits after PCB fabrication. FPGAs sit within the programmable logic hierarchy above CPLDs (Complex Programmable Logic Devices) and below ASICs in terms of integration density, belonging to the broader category of integrated circuits (ICs) and, more specifically, embedded ICs. Stratix II devices added adaptive logic modules (ALMs) to improve performance per logic element versus the original Stratix family.
Key features include dedicated DSP blocks for high-speed signal processing, embedded TriMatrix memory blocks, support for external memory interfaces including DDR/DDR2 SDRAM and QDRII SRAM, high-speed transceivers at up to 1 Gbps on applicable variants, and rich clock management via PLLs. The 780-FBGA package supports high I/O count with controlled-impedance signal routing.
Stratix II uses an ALM-based architecture that combines 8-input fracturable look-up tables (LUTs), dedicated carry chains, and distributed register files. The 90 nm process and adaptive routing fabric deliver high logic density with predictable timing closure, making the family well suited for data-path intensive designs such as protocol bridging, video processing, and high-speed serial interfaces.
Typical applications include telecommunications baseband and bridging equipment, high-performance DSP coprocessors, video and image processing pipelines, test and measurement instrumentation, and ASIC prototyping. The high logic capacity also fits network packet processing and storage controllers.
When designing with this device, pay close attention to power sequencing because Stratix II requires multiple supply rails (VCCINT, VCCIO, VCCA, VCCD_PLL). The 780-FBGA package demands careful PCB layout with buried vias or microvia technology on high-density boards to fan out the BGA escape routing.
This page synthesizes distributor pricing, same-package drop-in alternatives, and practical design notes that go beyond the manufacturer datasheet to accelerate board bring-up and sourcing decisions.
Аналоги без доработки для EP2S90F780C4 — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.
Варианты в этой серии
Модели той же серии, совместимые без доработки с EP2S90F780C4 (тот же форм-фактор и посадочное место) — отличается по Package, RoHS Status, Operating Temperature Grade, Family, Process Technology.
Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:
EP2S130F780C4
✅ Прямая замена✓ В наличии
$6500 / шт.
Открыть даташит →EP2S130F780C4N
✅ Прямая замена✓ В наличии
$1095 / шт.
Открыть даташит →EP2S60F672C4N
✅ Прямая замена✓ В наличии
$325 / шт.
Открыть даташит →EP2S90F1508C4
✅ Прямая замена✓ В наличии
$1320 / шт.
Открыть даташит →EP2S90F1020C4
✅ Прямая замена✓ В наличии
$1325 / шт.
Открыть даташит →EP2S130F780I4N
✅ Прямая замена✓ В наличии
$210 / шт.
Открыть даташит →EP2S90F780C4 Максимальные параметры и электрические характеристики
| Family | Stratix II |
| Manufacturer | Intel (formerly Altera) |
| Logic Elements | 90,960 |
| Logic Array Blocks (LABs) | 4,548 |
| Total RAM Bits | 4,520,488 |
| User I/Os | 534 |
| Process Technology | 90 nm |
| Core Supply Voltage | 1.15 V to 1.25 V |
| Operating Temperature Grade | Commercial (0C to +85C, suffix C4) |
| Корпус | 780-ball FBGA (FC-FBGA), 29 mm x 29 mm |
| Тип монтажа | Surface Mount |
| Packaging | Tray |
| Standard Pack Quantity | 36 |
| Статус RoHS | unknown |
| Speed Grade | C4 |
Руководство по цоколевке EP2S90F780C4 в корпусе 780-ball fbga (fc-fbga), 29 mm x 29 mm
Цоколевка для EP2S90F780C4 (корпус 780-ball fbga (fc-fbga), 29 mm x 29 mm). Эта цифровая ИС включает выводы GPIO, интерфейсы связи (UART, SPI, I2C) и выводы питания. Обратитесь к техническому описанию производителя для альтернативных функций выводов и вариантов конфигурации. Необходимо для проектирования встраиваемых систем и трассировки печатных плат.
Нет подробных данных о распиновке для EP2S90F780C4.
Обратитесь к даташиту для полной конфигурации выводов.
Типичное применение
EP2S90F780C4 подходит для 6 применениеs: Telecommunications Baseband Processing, ASIC Prototyping and Emulation, High-Performance DSP Coprocessor, Video and Image Processing Pipelines, Test and Measurement Instrumentation, Network Packet Processing and Storage Controllers.
Telecommunications Baseband Processing
The EP2S90F780C4's 90,960 logic elements and 4.5 Mbits of embedded RAM enable multi-channel baseband datapath implementations for legacy 3G/4G protocol stacks. Its 534 user I/Os connect to multiple external ADC/DAC pairs and high-speed memory buses such as DDR or QDRII SRAM. The Stratix II ALM architecture delivers predictable timing closure for parallel DSP chains required in turbo-decoder and rake-receiver designs. According to the Stratix II family datasheet, the device supports up to 12 embedded DSP blocks per row of LABs, enabling efficient implementation of FIR filters and correlators. The 780-FBGA package provides the high pin count needed to fan out 16+ parallel data lanes without external muxing.
Рекомендуется
ASIC Prototyping and Emulation
With 90,960 logic elements and 4,548 LABs, the EP2S90F780C4 can emulate ASIC designs in the 200K-300K gate range when mapped through Quartus II synthesis. The 4.5 Mbits of distributed TriMatrix memory allow realistic emulation of on-chip SRAM and register-file subsystems. Multiple EP2S90F780C4 devices can be paralleled via LVDS or external memory interfaces to scale to multi-million-gate ASIC prototypes. The 780-FBGA package provides the I/O bandwidth required to map large ASIC pins to FPGA I/Os. Designers benefit from Quartus II's incremental compilation to partition large ASIC designs across multiple Stratix II devices for hardware-software co-verification.
Рекомендуется
High-Performance DSP Coprocessor
The Stratix II DSP blocks deliver up to 450 MHz operation and support 18x18 multipliers with 36-bit accumulators. Combined with 90,960 LEs, the EP2S90F780C4 can implement multi-channel radar, sonar, or video processing pipelines in a single device. The 4.5 Mbits of embedded RAM feed DSP datapaths with zero wait-state access. The 780-FBGA package allows 534 user I/Os to interface with high-speed ADC/DAC banks and external DDR memory for sample buffering. Designers can chain multiple EP2S90F780C4 devices via LVDS links to scale channel count beyond a single FPGA's processing budget.
Рекомендуется
Video and Image Processing Pipelines
The EP2S90F780C4's logic capacity and embedded memory bandwidth make it suitable for HD-SDI video processing, real-time image filtering, and broadcast equipment designs. The 534 I/Os can carry multiple parallel video buses plus ancillary data and control channels. Embedded TriMatrix memory blocks serve as line buffers and frame store with sufficient depth for HD-resolution streams. The 780-FBGA package provides robust thermal performance at sustained high toggle rates required for multi-stream video processing. Quartus II's DSP Builder integration accelerates implementation of motion-estimation, scaling, and color-space conversion kernels.
Рекомендуется
Test and Measurement Instrumentation
The EP2S90F780C4 serves as the processing engine in high-end oscilloscopes, logic analyzers, and protocol testers requiring deep acquisition memory and flexible trigger logic. Its 4.5 Mbits of embedded RAM can buffer multi-million-sample captures, while 534 I/Os interface with high-speed ADCs, DACs, and probe front-ends. The 780-FBGA package supports the controlled-impedance signal integrity required for sub-nanosecond timing measurements. Designers use the Stratix II PLL blocks to generate precise multi-phase clocks for interleaved ADC sampling architectures.
Рекомендуется
Network Packet Processing and Storage Controllers
The EP2S90F780C4 implements wire-speed packet classification, deep-packet inspection, and RAID storage controllers in enterprise networking and storage equipment. The 90,960 LEs support large TCAM-equivalent lookup tables via distributed RAM, while 4.5 Mbits of block RAM buffer packet headers and descriptors. The 534 I/Os enable multiple SGMII / SPI-4.2 interfaces to network PHYs and SAS/SATA controllers. The 780-FBGA package's robust thermal envelope supports continuous high-traffic operation. Designers leverage Quartus II's QoS routing primitives to meet deterministic latency for time-critical control-plane traffic.
Рекомендуется
Сводка рекомендуемых товаров
Справочные инженерные данные для EP2S90F780C4 — сравнение, рекомендации по проектированию и информация о соответствии.
Руководство по выбору
Сравнение с аналогами
| Параметр | Этот товар | EP2S130F780C4 | EP2S130F780C4N | EP2S60F672C4N | EP2S130F780I4N |
|---|---|---|---|---|---|
| Package | 780-FBGA | 780-FBGA | 780-FBGA | 672-FBGA | 780-FBGA |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Family | Stratix II | Stratix II | Stratix II | Stratix II | Stratix II |
| Logic Elements | 90,960 | 132,540 | 132,540 | 60,440 | 132,540 |
| Total RAM Bits | 4,520,488 | 6,747,840 | 6,747,840 | 2,544,192 | 6,747,840 |
| Speed Grade | C4 | C4 | C4 | C4 | I4 (industrial) |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) |
Ключевые отличия
- Higher logic density in same 780-FBGA package (против EP2S60F672C4N)
- Industrial temperature grade variant available (против EP2S130F780I4N)
- Drop-in upgrade path within Stratix II family (против EP2S130F780C4)
Заметки по проектированию
The Stratix II EP2S90F780C4 requires four distinct supply rails: VCCINT (1.15-1.25 V core), VCCIO (per-bank I/O, typically 1.5/1.8/2.5/3.3 V), VCCA (1.5 V analog supply for PLLs), and VCCD_PLL (1.5 V digital PLL supply). Power-on sequencing must follow the Stratix II hardware reference design - typically VCCIO before VCCINT, with VCCA and VCCD_PLL ramped concurrently with VCCINT. Reverse sequencing risks device latch-up. Use a dedicated sequencer IC such as the LTC2923 rather than discrete RC delays.
The 780-FBGA package requires buried or microvia PCB technology for the inner ball rows to escape. A standard 4-layer board with through-vias cannot reliably escape signals from the inner BGA rows without via-in-pad cost. For prototypes, consider using the EP2S90F1508 variant in a larger BGA that allows through-via escape on standard 6-layer stackup. Floorplanning in Quartus II should match the BGA ball grid to the PCB escape pattern to avoid congestion.
Estimated: At full logic utilization (~80%) and 50% toggle rate with 1.2 V VCCINT and ~4 A core current, the EP2S90F780C4 may dissipate around 4.8 W from the core. Combined with I/O switching, total package dissipation can reach 6-8 W. The 780-FBGA's thermal pad and ball grid provide good thermal conduction to internal PCB copper planes; attach an internal copper flood of at least 1 oz copper over 4 layers to keep junction temperature below 100C. Forced airflow may be required in enclosed chassis.
Common pitfalls with the EP2S90F780C4 include: (1) failing to configure unused I/O pins as tri-stated inputs with weak pull-up via the Quartus II device options, (2) neglecting the configuration scheme selection (AS, AP, PS, FPP) which dictates the external PROM choice, (3) underestimating JTAG chain timing when multiple Stratix II devices share a TCK, and (4) ignoring the I/O bank VCCIO grouping constraints which can force awkward PCB routing if not planned during floorplan.
Информация о соответствии
Compliance status not explicitly stated in the verified web data. The N-suffixed variants (e.g. EP2S90F780C4N) would typically be lead-free, but the C4 suffix here does not include the lead-free indicator. Verify with distributor documentation before use in RoHS-restricted regions.
