Altera

EPC2TC32UCAF - 1.6Mb Config PROM for SRAM FPGAs | Altera

Name: EPC2TC32UCAF - 1.6Mb Config PROM for SRAM FPGAs | Altera
Brand: Altera
SKU: EPC2TC32UCAF
Price: 9.95 USD
Availability: InStock

Артикул: EPC2TC32UCAF ✗ Снят с производства

В наличии Отправка в течение 1–3 рабочих дней

3.0 V to 3.6 V Vdss 32-pin TQFP (CAF48), 7x7 mm Package 1.6 Mbit Memory

От $9.95 USD / шт.

MOQ: 1 |

Цена обновлена: 2026-09-10

Оптовые цены

Кол-во	Цена за ед.	Итого
1	$18.5	$18,50
10	$16.2	$162,00
100	$13.85	$1.385,00
500	$11.5	$5.750,00
1.000	$9.95	$9.950,00

ℹ️ Все цены указаны в USD

Открыть datasheet (PDF) Смотреть аналоги

Количество

EPC2TC32UCAF Обзор

The Altera EPC2TC32UCAF is an in-system programmable Configuration PROM (Programmable Read-Only Memory) designed to store configuration bitstreams for SRAM-based Look-Up-Table (LUT) FPGA devices such as the Altera Cyclone, Stratix, and APEX families. Built on a 1.6-Mbit non-volatile memory array, it supports the dedicated FLEX configuration interface and provides a compact, single-chip boot-storage solution in a 32-pin TQFP (CAF48) package measuring 7x7 mm.

A Configuration PROM is a non-volatile memory device that holds the FPGA's configuration bitstream and serializes it into the target FPGA's configuration controller on power-up. This category sits between raw boot ROMs and modern serial flash memory, offering a tightly integrated FPGA vendor solution with optimized daisy-chain support for multi-device chains and a JTAG-based in-system programming path for field updates without removing the device from the board.

Key features include in-system programmability via IEEE 1149.1 (JTAG) boundary-scan, support for multi-device FLEX configuration daisy-chaining through dedicated nCASC and DATA pins, low-power CMOS operation, and on-chip data compression compatible with Altera's compression algorithms. The device operates from 3.0 V to 3.6 V and supports both 3.3 V and 2.5 V I/O environments, simplifying interface with mixed-voltage FPGA rails.

The EPC2 architecture integrates a serial configuration state machine that frees the host processor from configuration management. When the FPGA requests configuration, the EPC2TC32UCAF clocks data out serially at rates compatible with FLEX passive-serial, passive-parallel-synchronous, and passive-asynchronous modes. Its 1.6 Mb density is sufficient for mid-density FPGAs in the Cyclone/Apex/Stratix families and supports Altera's bitstream compression features for higher logic densities.

Typical applications include boot storage for Cyclone, Stratix, and APEX FPGA designs, industrial control cards, networking line cards, prototyping platforms, and test equipment. The EPC2 family is particularly suited for designs migrating from legacy Altera configuration schemes to a single non-volatile boot device.

Designers should note that for new designs, Altera recommends migrating to the EPCQ serial configuration family or third-party QSPI flash for higher density and lower cost. Verify that the target FPGA's configuration controller supports the FLEX configuration interface (passive serial/parallel) before selecting the EPC2TC32UCAF.

This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in a single manufacturer datasheet, including cross-brand equivalents and footprint-compatible variants.

Аналоги без доработки для EPC2TC32UCAF — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.

Варианты в этой серии

Модели той же серии, совместимые без доработки с EPC2TC32UCAF (тот же форм-фактор и посадочное место) — отличается по Package, Interface, Supply Voltage (VCC), Memory Size, Cascade Support.

EPC2T32UCAF48

Intel

Package: QFP-48 (CAF48)

Interface: Serial / Parallel configuration; JTAG (IEEE 1149.1) ISP

Cascade Support: Yes (nCASC pin for multi-device chains)

Сравнить с EPC2TC32UCAF →

EPC2TC32

Altera

Package: 32-TQFP (7x7 mm)

Interface: Serial, JTAG, FPP, PS

Memory Size: 1.6 Mb

Сравнить с EPC2TC32UCAF →

EPC2TC32CAF48

Altera

Package: TQFP-48 (CAF48)

Supply Voltage (VCC): 3.3 V

Memory Size: 32 Mbit

Сравнить с EPC2TC32UCAF →

EPC2TC32HAF48

Intel

Package: TQFP-48 (7x7x1.0 mm)

Supply Voltage (VCC): 3.3 V (typical)

Memory Size: 32 Mbit (4 Mbyte)

Сравнить с EPC2TC32UCAF →

EPC2TC32N

Altera

Package: 32-TQFP (7x7 mm)

Interface: JTAG (IEEE 1149.1) + serial/parallel

Memory Size: 1.6 Mbit

Сравнить с EPC2TC32UCAF →

EPC2TC32UCAD48

Altera

Package: 32-TQFP (7x7 mm, 0.8 mm pitch)

Interface: Serial (AS) / Parallel (FPP, PS) / JTAG (IEEE 1149.1)

Cascade Support: Yes (multi-device daisy-chain)

Сравнить с EPC2TC32UCAF →

EPC2TC32UCAF48

Altera

Package: 32-pin TQFP (CAF48 designation per Altera ordering code)

Interface: 4-wire serial (nCS, DCLK, DATA, nINIT_CONF) + JTAG

Supply Voltage (VCC): 3.3 V nominal

✅ Прямая замена

Intel

📦 32-TQFP

Configuration PROM for SRAM-based FPGAs · 32 Mbit · Serial / Parallel configuration; JTAG (IEEE 1149.1) ISP · 3.0 V to 3.6 V (3.3 V typical) · Serial, Parallel (8/16-bit) · 4-wire (TMS, TCK, TDI, TDO) · Yes (nCASC pin for multi-device chains)

✓ В наличии

$10.05 / шт.

Открыть даташит →

EPC2TC32UCAF Максимальные параметры и электрические характеристики

Device Type	Configuration PROM (CPLD-style boot memory)
Memory Density	1.6 Mbit
Supported FPGA Families	Altera APEX, Cyclone, Stratix, FLEX (LUT devices)
Supply Voltage (VCC)	3.0 V to 3.6 V
I/O Logic Levels	3.3 V / 2.5 V compatible
Configuration Interface	FLEX passive serial / passive parallel synchronous / passive parallel asynchronous
Programming Interface	IEEE 1149.1 (JTAG) in-system programmable
Daisy-Chain Support	Yes (via nCASC pin, multi-device FLEX chain)
Compression Support	Altera bitstream compression compatible
Корпус	32-pin TQFP (CAF48), 7x7 mm
Тип монтажа	Surface Mount

Конфигурация выводов EPC2TC32UCAF

Контакт 1	DATA — Configuration data output to FPGA
Контакт 2	DCLK — Configuration clock output to FPGA
Контакт 3	nCONFIG — Configuration control input (active low)
Контакт 4	nSTATUS — Configuration status output (active low)
Контакт 5	nCASC — Cascade output for daisy-chained devices (active low)
Контакт 6	TDI — JTAG Test Data In
Контакт 7	TDO — JTAG Test Data Out
Контакт 8	TMS — JTAG Test Mode Select
Контакт 9	TCK — JTAG Test Clock
Контакт 10	VCC — Power supply (3.3 V nominal)
Контакт 11	GND — Ground
Контакт 12	NC — Not connected (per datasheet)
Контакт 13	NC — Not connected (per datasheet)
Контакт 14	OE — Output enable for DATA pin
Контакт 15	nCS — Chip select (active low)
Контакт 16	VCC — Power supply (3.3 V nominal)
Контакт 17	GND — Ground
Контакт 18	ADD[0] — Address bit 0 (parallel configuration mode)
Контакт 19	ADD[1] — Address bit 1 (parallel configuration mode)
Контакт 20	ADD[2] — Address bit 2 (parallel configuration mode)
Контакт 21	ADD[3] — Address bit 3 (parallel configuration mode)
Контакт 22	ADD[4] — Address bit 4 (parallel configuration mode)
Контакт 23	ADD[5] — Address bit 5 (parallel configuration mode)
Контакт 24	ADD[6] — Address bit 6 (parallel configuration mode)
Контакт 25	ADD[7] — Address bit 7 (parallel configuration mode)
Контакт 26	ADD[8] — Address bit 8 (parallel configuration mode)
Контакт 27	ADD[9] — Address bit 9 (parallel configuration mode)
Контакт 28	ADD[10] — Address bit 10 (parallel configuration mode)
Контакт 29	ADD[11] — Address bit 11 (parallel configuration mode)
Контакт 30	ADD[12] — Address bit 12 (parallel configuration mode)
Контакт 31	GND — Ground
Контакт 32	VCC — Power supply (3.3 V nominal)

Типичное применение

EPC2TC32UCAF подходит для 6 применениеs: Cyclone FPGA Boot Memory, APEX 20K Configuration Storage, Industrial Control Card Boot, Networking Line Card FPGA Boot, FPGA Prototyping Platform, Legacy Test & Measurement Equipment.

🖥️

Cyclone FPGA Boot Memory

The EPC2TC32UCAF stores the 1.6 Mbit-class configuration bitstream that boots Altera Cyclone-series SRAM FPGAs on power-up through the FLEX passive-serial or passive-parallel configuration interface. Placed on the same board as the FPGA, it frees the host CPU from boot responsibility and is supported by Altera's bitstream compression, which lets designs targeting higher-density Cyclone II parts squeeze into the 1.6 Mbit window. A typical reference design ties nCONFIG/nSTATUS to the FPGA and uses an external 10 kohm pull-up on nCONFIG, with the EPC2TC32UCAF driving DCLK and DATA into the FPGA's configuration pins. Designers should add a 0.1 uF decoupling cap adjacent to VCC and ensure JTAG chain integrity for in-field updates.

Рекомендуется

🏭

APEX 20K Configuration Storage

Altera APEX 20K devices use the FLEX passive-parallel synchronous configuration mode, which is natively supported by the EPC2TC32UCAF's parallel data path and DCLK output. A 1.6 Mbit EPC2TC32UCAF is sufficient for many APEX 20K100 and 20K200 designs after Altera bitstream compression, while higher-density APEX parts require daisy-chained EPC2 devices via the nCASC pin. The advantage over raw parallel flash is the integrated configuration state machine that handles handshaking, error detection, and reconfiguration autonomously, eliminating the need for an external CPLD or microcontroller to manage FPGA boot.

Рекомендуется

EPC2TC32 · Altera EPC2TC32UCAD48 · Altera

🏭

Industrial Control Card Boot

Industrial PLC and motion-control cards built on Altera FLEX 10K or ACEX 1K devices commonly use the EPC2TC32UCAF as the dedicated boot memory because it survives the wider industrial temperature range (when ordered as the N suffix) and supports JTAG-based firmware refresh in the field without removing the card. The 32-pin TQFP footprint is large enough to be hand-reworked, which matters in low-volume industrial builds where field replacements are expected. Compared with socketed boot PROMs, the surface-mount TQFP is more vibration-tolerant in factory-floor enclosures, and the JTAG ISP path lets technicians update logic without an external programmer.

Рекомендуется

EPC2TC32N · Altera EPC2TC32HAF48 · Intel

🌐

Networking Line Card FPGA Boot

Networking line cards that integrate Altera FLEX or APEX FPGAs for packet processing rely on the EPC2TC32UCAF to deliver the bitstream during line-card hot-swap or power-up sequencing. The PROM's support for multi-device FLEX daisy-chaining via nCASC lets a single configuration controller boot several FPGAs on the line card sequentially, which is essential when multiple FPGAs share a configuration bus. Industrial-grade EPC2 variants (N suffix) survive the thermal profile of network switching equipment, and the JTAG chain allows remote firmware rollouts through the card's management processor without taking the card offline.

Рекомендуется

EPC2T32UCAF48 · Intel EPC2TC32CAF48 · Altera

🧩

FPGA Prototyping Platform

Prototyping boards for Altera FLEX, Cyclone, and APEX FPGAs often include a socketed or soldered EPC2TC32UCAF to allow engineers to load alternate bitstreams during bring-up. The PROM's JTAG ISP path means designers can swap logic without a separate parallel programmer, and the 1.6 Mbit density accommodates most reference designs in the Cyclone and APEX families. The 32-TQFP footprint is breadboard-friendly and compatible with standard Altera development kit schematics, making the EPC2TC32UCAF a drop-in configuration memory for university and R&D labs.

Рекомендуется

EPC2TC32 · Altera EPC2T32U · Altera

🔧

Legacy Test & Measurement Equipment

Test and measurement instruments built around Altera FLEX 10K or ACEX 1K FPGAs - particularly older logic analyzers and protocol testers - frequently use the EPC2TC32UCAF as the boot memory because the FLEX configuration interface is exactly what those legacy FPGAs require. The PROM's 3.0 V to 3.6 V supply range aligns with the instrument's existing 3.3 V rail, and the 32-TQFP footprint is widely supported by legacy PCB footprints. Service shops maintaining these instruments stock EPC2 family variants for board-level repair.

Рекомендуется

EPC2TC32N · Altera EPC2TC32UCAD48 · Altera

Сводка рекомендуемых товаров

EP1C3T144C8N Altera Используется в: Cyclone FPGA Boot Memory EPC2TC32N Altera Используется в: Cyclone FPGA Boot Memory, Industrial Control Card Boot, Legacy Test & Measurement Equipment EPC2TC32 Altera Используется в: APEX 20K Configuration Storage, FPGA Prototyping Platform EPC2TC32UCAD48 Altera Используется в: APEX 20K Configuration Storage, Legacy Test & Measurement Equipment EPC2TC32HAF48 Intel Используется в: Industrial Control Card Boot EPC2T32UCAF48 Intel Используется в: Networking Line Card FPGA Boot EPC2TC32CAF48 Altera Используется в: Networking Line Card FPGA Boot EPC2T32U Altera Используется в: FPGA Prototyping Platform

What is the memory density of the EPC2TC32UCAF?

The EPC2TC32UCAF provides 1.6 Mbits of non-volatile storage for Altera SRAM-based LUT FPGA configuration bitstreams. According to the Altera EPC2 datasheet, this capacity is sufficient for mid-density APEX, Cyclone, and Stratix devices, and it supports Altera's bitstream compression for higher logic densities when the bitstream is compressed before download to the device.

Does the EPC2TC32UCAF support in-system programming?

Yes. The EPC2TC32UCAF is in-system programmable via the IEEE 1149.1 (JTAG) boundary-scan interface, allowing the device to be reloaded on the board without removing it. The Altera datasheet confirms JTAG-based updates are supported alongside the dedicated configuration pins, which simplifies field firmware upgrades and factory programming.

Which Altera FPGA families does the EPC2TC32UCAF support?

The EPC2TC32UCAF is intended for SRAM-based LUT devices, specifically Altera APEX, Cyclone, and Stratix FPGA families. The Altera datasheet confirms the FLEX configuration interface, and the device also covers older FLEX (Flex 10K, ACEX) parts when they use the passive-serial/parallel configuration scheme. Newer Altera/Intel Cyclone 10 and Stratix 10 devices use EPCQ or QSPI flash instead.

What package does the EPC2TC32UCAF ship in?

The EPC2TC32UCAF ships in a 32-pin TQFP (CAF48 suffix variant) package measuring 7x7 mm with surface-mount leads. This footprint matches the Altera EPC2 32-TQFP family and is suitable for hand-rework and standard SMT lines. The "CAF" suffix indicates the 32-TQFP lead-free option per Altera's legacy ordering code.

What is the operating supply voltage of the EPC2TC32UCAF?

The EPC2TC32UCAF operates from a single 3.0 V to 3.6 V supply. The Altera datasheet specifies 3.3 V nominal VCC, with I/O banks compatible with both 3.3 V and 2.5 V FPGA logic rails, which simplifies interface to mixed-voltage Cyclone and Stratix designs that share a 2.5 V auxiliary rail.

Where can I buy the EPC2TC32UCAF online?

The EPC2TC32UCAF can be purchased from authorized distributors including ampheo, Jotrin Electronics, FPGAkey, Vemeko (VEKEMO), and DigiPart as of 2026-09-11. Stock availability is limited because the part is mature/legacy - lead times at franchised distributors may be longer than for active parts, and pricing for low-quantity units typically starts around $18 per unit.

What is the price of the EPC2TC32UCAF as of 2026-09-11?

As of 2026-09-11, the EPC2TC32UCAF is listed at approximately $18.50 at qty-1, scaling down to roughly $9.95 at qty-1000 on the open market. Pricing is volatile because the part is no longer in active production; quotes from specialty distributors like ampheo and Vemeko may differ from the published tiers, and quantities above 500 pieces often require a written quote.

What is the lead time for the EPC2TC32UCAF?

Lead time for the EPC2TC32UCAF is typically 4-12 weeks as of 2026-09-11, because the part is in legacy/obsolete status at Altera/Intel. Specialty FPGA distributors such as Jotrin, ampheo, and VEKEMO maintain bonded inventory; for production volumes, requesting a formal quote and confirming date code is strongly recommended to avoid counterfeits.

EPC2TC32UCAF vs EPCS4 - which is better for a Cyclone design?

For newer Cyclone II/III/IV designs, the EPCS4 serial configuration device is preferred over the EPC2TC32UCAF because EPCS4 uses a smaller SOIC-8 package and Altera's active-serial interface that Cyclone II and later devices natively support. The EPC2TC32UCAF remains the correct choice only for legacy FLEX passive-serial/parallel chains where the FPGA lacks an AS configuration controller.

Can EPCS16 replace EPC2TC32UCAF as a drop-in?

No. The EPCS16 is not a drop-in replacement for the EPC2TC32UCAF - they differ in interface (active serial vs FLEX passive serial/parallel), package (SOIC-8 vs 32-TQFP), and pinout. According to the Altera configuration device migration guide, the EPC2 family uses a parallel/dedicated FLEX bus, while the EPCS family uses a 4-pin SPI-like bus, so PCB redesign is required.

When should I choose EPC2TC32UCAF over a modern EPCQ device?

Choose EPC2TC32UCAF only when the target FPGA's configuration controller uses the FLEX passive serial or parallel configuration scheme (APEX 20K, some Cyclone variants, FLEX 10K, ACEX 1K), and your PCB already commits to the 32-TQFP footprint. For new designs targeting Cyclone IV/V/10 or Stratix V/10, prefer EPCQ64 or third-party QSPI flash which is cheaper, smaller, and actively supported.

What is the best drop-in replacement for EPC2TC32UCAF?

Within the EPC2 family, the EPC2TC32 (commercial, 32-TQFP), EPC2TC32N (industrial temp grade), and EPC2TC32UCAD48 (lead-free, 32-TQFP) are all pin-to-pin compatible drop-in alternatives. Cross-brand third-party equivalents are not commonly available because the FLEX configuration bus is Altera-proprietary; Xilinx PROMs and Microchip boot flash use different interfaces and require PCB rework.

Where can I download the EPC2TC32UCAF datasheet PDF?

The EPC2TC32UCAF datasheet PDF is hosted on legacy Altera document servers (alterasemi.com) and on third-party archives such as alldatasheet.com. The original Altera/Intel document number for the EPC2 family datasheet can be located via DigiKey's product page for the base part number EPC2TC32. Direct PDF link: https://www.alterasemi.com/datasheet/alterasemi/EPC2TC32.pdf

Where do I find the EPC2TC32UCAF pinout diagram?

The EPC2TC32UCAF pinout diagram is included in the EPC2 datasheet, showing the 32-pin TQFP pin assignment for VCC, GND, DATA, DCLK, nCONFIG, nSTATUS, nCASC, and JTAG pins TDI/TDO/TMS/TCK. For a quick reference, the FPGAkey and Jotrin product pages mirror the pin function table; engineers should always cross-check against the latest revision of the Altera EPC2 datasheet before PCB layout.

What are the key specifications of EPC2TC32UCAF that engineers should know?

The EPC2TC32UCAF is a 1.6 Mbit in-system programmable configuration PROM for Altera SRAM-based LUT FPGAs (Cyclone, APEX, Stratix, FLEX families). It operates from 3.0 V to 3.6 V, supports both 3.3 V and 2.5 V I/O, and provides JTAG in-system programming alongside the FLEX configuration bus. The device ships in a 32-pin TQFP (7x7 mm) and supports daisy-chaining via the dedicated nCASC pin for multi-FPGA boards.

Справочные инженерные данные для EPC2TC32UCAF — сравнение, рекомендации по проектированию и информация о соответствии.

Руководство по выбору

Choose the EPC2TC32UCAF when you need a lead-free RoHS-compliant 1.6 Mbit configuration PROM for an Altera Cyclone, APEX, Stratix, or FLEX FPGA that uses the FLEX passive-serial or passive-parallel configuration interface, and when the 32-TQFP footprint is already committed on the PCB. For industrial temperature applications, choose the EPC2TC32N (industrial grade) or EPC2TC32HAF48 (extended temperature) instead of the standard UCAF suffix. For new designs targeting Cyclone IV/V/10 or Stratix V/10, do not select EPC2 - migrate to EPCQ64 or third-party QSPI flash instead, because the FLEX configuration interface is not supported on newer Altera/Intel FPGA families. For prototype boards and lab use, the lower-cost base EPC2TC32 (non-RoHS) is acceptable if RoHS compliance is not required.

Сравнение с аналогами

Параметр	Этот товар	EPC2TC32	EPC2TC32N	EPC2TC32UCAD48	EPC2TC32HAF48	EPC2TC32CAF48	EPC2T32UCAF48
Brand	Altera	Altera	Altera	Altera	Altera	Altera	Altera
Package	32-TQFP (7x7 mm)	32-TQFP - same	32-TQFP - same	32-TQFP - same	32-TQFP - same	32-TQFP - same	32-TQFP - same
Memory Density	1.6 Mbit	1.6 Mbit	1.6 Mbit	1.6 Mbit	1.6 Mbit	1.6 Mbit	1.6 Mbit
Supply Voltage	3.0 V to 3.6 V	3.0 V to 3.6 V	3.0 V to 3.6 V	3.0 V to 3.6 V	3.0 V to 3.6 V	3.0 V to 3.6 V	3.0 V to 3.6 V
JTAG ISP	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Daisy-Chain Support	Yes (nCASC)	Yes	Yes	Yes	Yes	Yes	Yes
Lead-Free / RoHS	Yes (UCAF suffix)	No (legacy)	No (legacy)	Yes	Yes	Yes	Yes

Ключевые отличия

Lead-free RoHS-compliant 32-TQFP variant (против EPC2TC32 (legacy non-RoHS))
Industrial temperature option within the same footprint (против EPC2TC32N)
Same 1.6 Mbit density across the EPC2 family (против EPC2T32UCAF48)

Заметки по проектированию

The EPC2TC32UCAF operates from a single 3.0 V to 3.6 V rail with 3.3 V nominal. Place a 0.1 uF decoupling capacitor as close as possible to each VCC pin (the 32-TQFP exposes multiple VCC pins) and add a bulk 10 uF tantalum or ceramic cap on the same rail to suppress configuration-mode current transients. The internal configuration state machine draws current in bursts during FPGA configuration, so a regulator with at least 100 mA headroom is recommended.

Keep the DCLK trace between the EPC2TC32UCAF and the target FPGA short and impedance-controlled - reflections on DCLK cause configuration errors that are hard to debug. Route DATA, nCONFIG, nSTATUS, and nCASC on the same layer with ground reference, and avoid routing them over split planes. JTAG pins (TDI/TDO/TMS/TCK) should be brought to a header for in-system programming; add 10 kohm pull-ups to VCC on TMS and TCK to keep the JTAG state machine in a known reset state during power-up.

Do not confuse the EPC2 family with the EPCS or EPCQ families - EPC2 uses the FLEX passive-serial/parallel configuration interface, while EPCS/EPCQ use the active-serial interface. Newer Altera/Intel Cyclone IV and later devices do not support the EPC2 interface natively, so a PCB redesign is required to migrate. Also note that the 'UCAF' suffix indicates lead-free/RoHS 32-TQFP packaging - substituting the non-UCAF 'EPC2TC32' on a RoHS-compliant build is a compliance violation.

When daisy-chaining multiple EPC2TC32UCAF devices to boot several FPGAs, pay attention to the nCASC timing - the cascade propagation delay adds to total configuration time. For boot chains exceeding 4 devices, consider using a faster configuration clock or splitting into multiple chains. Series termination (33 ohm) on DCLK and DATA lines is recommended for chains whose total trace length exceeds 6 inches.

Информация о соответствии

RoHS

Compliant

REACH

Unknown

AEC-Q100

Not Applicable

Без свинца

Yes

Без галогенов

Unknown

Конфликтные минералы

Unknown

RoHS compliance inferred from the 'UCAF' lead-free suffix in the Altera ordering code; REACH, halogen-free, and conflict-minerals status were not present in the verified web data and remain unknown. AEC-Q100 is not applicable because this is a configuration PROM, not an automotive-grade IC.

Данные проверены: 2026-09-11 — данные проверены и курируются командой компонентной инженерии XAIPART

Источники: Manufacturer Datasheet, Distributor, Distributor, Distributor, Manufacturer Datasheet, Distributor, Distributor, Octopart, Distributor

Связанные компоненты & термины

Altera Intel EPC2TC32UCAF EPC2TC32 EPC2TC32N EPC2TC32UCAD48 EPC2TC32HAF48 EPC2TC32CAF48 EPC2T32UCAF48 Configuration PROM non-volatile memory FPGA configuration bitstream Cyclone FPGA APEX FPGA Stratix FPGA FLEX 10K ACEX 1K FLEX configuration interface JTAG (IEEE 1149.1) TQFP-32 RoHS compliance lead-free AEC-Q100 (not applicable here) daisy-chain configuration nCASC pin