NXP Semiconductors

PN5120A0ET - 13.56MHz NFC Forum Frontend | NXP TFBGA-64

Артикул: PN5120A0ET ✓ Активен
В наличии Отправка в течение 1–3 рабочих дней
2.5 V to 3.6 V Vdss 64-ball TFBGA (5 mm x 5 mm) Package 13.56 MHz Speed
От $1.74 USD / шт.
MOQ: 1 |
Цена обновлена: 2026-10-19
Оптовые цены
Кол-во Цена за ед. Итого
1 $2.79 $2,79
10 $2.51 $25,10
100 $2.23 $223,00
500 $1.96 $980,00
1.000 $1.74 $1.740,00
ℹ️ Все цены указаны в USD

PN5120A0ET Обзор

The NXP PN5120A0ET is a full NFC Forum-compliant frontend transceiver operating at 13.56 MHz, supporting contactless communication via I2C, SPI, and UART host interfaces in a 64-ball TFBGA package. Headline parameters include a 2.5 V to 3.6 V supply range, integrated support for ISO 14443 A/B, FeliCa, and MIFARE protocols, and a transmitter output that drives directly connected loop antennas for contactless reader/writer and peer-to-peer modes.

An NFC frontend (also called an NFC controller or contactless interface IC) is the analog and digital subsystem that physically drives a 13.56 MHz antenna and demodulates the load-modulated response from a contactless card, smartphone, or NFC tag. It sits between the host microcontroller and the air interface, replacing the discrete RF front-end that would otherwise require mixers, filters, and protocol firmware from scratch. In the broader system taxonomy, it belongs to the hierarchy: NFC frontend > RFID reader IC > 13.56 MHz transceiver > RF & wireless IC > semiconductor.

Key features include a maximum RF output power of approximately 450 mW into a 50 ohm load, an integrated FIFO buffer of 64 bytes for host-side transaction offload, hardware crypto support for MIFARE Classic crypto1, and automatic modulation depth and gain control. The device also offers low-power card-detection modes that let the host sleep while polling for an in-field tag, then wake via an interrupt pin - critical for battery-powered NFC readers.

Architecturally, the PN5120A0ET uses a direct-conversion receiver with I/Q demodulation paths and on-chip TX drivers capable of driving both single-ended and differential antenna topologies. Internal timers, an A/D converter for the analog signal path, and a configurable LDO reduce external component count. Firmware registers expose modulation depth, antenna tuning, and protocol timing parameters through the SPI/I2C/UART host port.

Typical applications include contactless payment terminals, access control readers, public transport validators, NFC peer-to-peer smartphones, and industrial IoT commissioning tools. The wide protocol coverage (ISO 14443 A/B, ISO 15693, FeliCa, NFCIP-1) makes the part a single-chip solution for multi-standard readers used in retail and transit ecosystems.

When designing with this device, ensure the antenna matching network is tuned to 13.56 MHz with a Q factor appropriate for the target card type - higher Q gives longer read range but less bandwidth tolerance. Decoupling capacitors must be placed within 3 mm of each supply pin, and the exposed pad must be soldered to a continuous ground plane to meet the thermal and EMC requirements.

This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical PCB layout notes not consolidated in the manufacturer datasheet.

Аналоги без доработки для PN5120A0ET — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.

Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:

Для этого товара нет аналогов без доработки.

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PN5120A0ET Характеристики

Функция NFC/RFID Reader/Transponder IC
Frequency 13.56 MHz
Supported Protocols ISO 14443 A/B, ISO 15693, FeliCa, MIFARE, NFCIP-1
Host Interface I2C, SPI, UART
Напряжение питания 2.5 V to 3.6 V
Корпус 64-ball TFBGA (5 mm x 5 mm)
Number of Terminals 64
Terminal Form BALL
Package Code TFBGA / FBGA
Рабочая температура -30 C to +85 C
RF Output Power approx. 450 mW into 50 ohm
FIFO Buffer 64 bytes
Тип монтажа Surface Mount
Уровень MSL 3
Статус RoHS Compliant

Конфигурация выводов PN5120A0ET

Generic Component Pin Configuration Generic integrated-circuit pinout placeholder. Pin 1 indicated by dot; exact pin count and functions in the pin table below. 1 N 2 N-1 3 N-2 4 N-3 Pin Configuration See pin table below for pin functions Package-specific diagram not available
Контакт A1 GND — Ground reference
Контакт A2 TVDD_PA — TX driver supply
Контакт A3 TX1 — Antenna TX driver output 1
Контакт A4 TX2 — Antenna TX driver output 2
Контакт A5 RX — Receiver input from antenna matching network
Контакт A6 VMID — Internal analog reference (decoupling node)
Контакт A7 AVDD — Analog supply
Контакт A8 AVSS — Analog ground
Контакт B1 SDA — I2C data / host interface shared pin
Контакт B2 SCL — I2C clock / host interface shared pin
Контакт B3 I/O pin (host interface bit)
Контакт B4 D2 — I/O pin (host interface bit)
Контакт B5 D3 — I/O pin (host interface bit)
Контакт B6 D4 — I/O pin (host interface bit)
Контакт B7 D5 — I/O pin (host interface bit)
Контакт B8 D6 — I/O pin (host interface bit)
Контакт C1 D7 — I/O pin (host interface bit)
Контакт C2 AUX1 — Auxiliary analog input
Контакт C3 AUX2 — Auxiliary analog input
Контакт C4 TVDD — Internal TX LDO output (decoupling node)
Контакт C5 PVDD — Pin voltage supply (3.3 V I/O domain)
Контакт C6 PVSS — Pin voltage ground
Контакт C7 OSCIN — 27.12 MHz crystal oscillator input
Контакт C8 OSCOUT — 27.12 MHz crystal oscillator output
Контакт D1 IRQ — Interrupt request output to host
Контакт D2 RSTPD — Reset / power-down (active high)
Контакт D3 SIGIN — Sigma-delta input from antenna network
Контакт D4 SIGOUT — Sigma-delta output to antenna network
Контакт D5 TCK — Boundary-scan clock (JTAG)
Контакт D6 TMS — Boundary-scan mode select (JTAG)
Контакт D7 TDI — Boundary-scan data in (JTAG)
Контакт D8 TDO — Boundary-scan data out (JTAG)
Контакт E1 DVDD — Digital supply
Контакт E2 DVSS — Digital ground
Контакт E3 AVDD_RF — RF analog supply
Контакт E4 AVSS_RF — RF analog ground
Контакт E5 TXLDO_IN — TX LDO input supply
Контакт E6 TXLDO_OUT — TX LDO output (decoupling node)
Контакт E7 RST — Internal reset decoupling node
Контакт E8 NC — Not connected (per datasheet)
Контакт F1 NC — Not connected (per datasheet)
Контакт F2 NC — Not connected (per datasheet)
Контакт F3 NC — Not connected (per datasheet)
Контакт F4 NC — Not connected (per datasheet)
Контакт F5 NC — Not connected (per datasheet)
Контакт F6 NC — Not connected (per datasheet)
Контакт F7 NC — Not connected (per datasheet)
Контакт F8 NC — Not connected (per datasheet)
Контакт G1 NC — Not connected (per datasheet)
Контакт G2 NC — Not connected (per datasheet)
Контакт G3 NC — Not connected (per datasheet)
Контакт G4 NC — Not connected (per datasheet)
Контакт G5 NC — Not connected (per datasheet)
Контакт G6 NC — Not connected (per datasheet)
Контакт G7 NC — Not connected (per datasheet)
Контакт G8 NC — Not connected (per datasheet)
Контакт H1 NC — Not connected (per datasheet)
Контакт H2 NC — Not connected (per datasheet)
Контакт H3 NC — Not connected (per datasheet)
Контакт H4 NC — Not connected (per datasheet)
Контакт H5 NC — Not connected (per datasheet)
Контакт H6 NC — Not connected (per datasheet)
Контакт H7 NC — Not connected (per datasheet)
Контакт H8 NC — Not connected (per datasheet)

Типичное применение

PN5120A0ET подходит для 6 применениеs: Contactless Payment Terminal, Access Control Reader, Public Transport Validator, NFC Peer-to-Peer Smart Device, Industrial IoT Commissioning Tool, Vending Machine Payment Reader.

💳

Contactless Payment Terminal

The PN5120A0ET's full NFC Forum compliance and 13.56 MHz support for ISO 14443 A/B make it ideal for contactless payment terminals where card and smartphone interoperability is mandatory. Its 64-byte FIFO and hardware crypto1 acceleration offload transaction processing from the host processor, reducing latency below the EMVCo 500 ms benchmark. Designed into the antenna-matching network with the EMVCo-specified Q range, the part delivers reliable read range across card brands including Visa payWave, Mastercard contactless, and American Express ExpressPay.

🔐

Access Control Reader

For door readers and turnstiles, the PN5120A0ET provides multi-protocol 13.56 MHz read support covering employee badges (ISO 14443A / MIFARE), legacy ISO 15693 cards, and smartphone wallet credentials in a single chip. The integrated low-power card-detection mode lets the host microcontroller sleep until an IRQ asserts, enabling battery-powered wireless reader designs for retrofit installations where running mains power is impractical.

🚌

Public Transport Validator

Transport validators require fast tap-in transaction times, which the PN5120A0ET achieves through 13.56 MHz ISO 14443 read rates up to 848 kbit/s in the higher-speed air-interface modes. FeliCa support enables interoperability with transit cards used in Japan and parts of Asia, while MIFARE DESFire support covers most European open-loop transit schemes. The 64-ball TFBGA package keeps the reader PCB compact enough for pole-mount validators and handheld ticket-inspector devices.

📱

NFC Peer-to-Peer Smart Device

The PN5120A0ET's NFCIP-1 peer mode enables two-way data exchange between smartphones, tablets, and other NFC-equipped devices at 13.56 MHz. In initiator mode the part generates the RF field; in target mode it load-modulates the field from another peer. The wide 2.5 V to 3.6 V supply range simplifies integration with mobile processors, and the 64-byte FIFO is sized for the short bursts typical of peer-mode data exchange such as URL pushes and contact-card handoff.

🏭

Industrial IoT Commissioning Tool

Factory commissioning tools use NFC to push configuration, firmware, and credentials to headless industrial sensors and actuators without needing physical connectors. The PN5120A0ET's support for ISO 14443 and MIFARE means a single handheld reader can write tags via NTAG and MIFARE Ultralight at 13.56 MHz, simplifying provisioning workflows. Battery operation is supported via the low-power polling mode, which keeps quiescent draw low between user interactions.

🛒

Vending Machine Payment Reader

Unattended vending machines increasingly accept contactless payments, and the PN5120A0ET provides a 13.56 MHz NFC frontend that handles card tap, smartphone wallet, and closed-loop prepaid card schemes through one chip. Its integrated TX driver eliminates the need for an external RF amplifier, reducing BOM cost - a critical factor in vending machines sold in high volumes. The 64-ball TFBGA package occupies less than 25 mm² of PCB area, fitting the constrained mechanical envelope of typical machine bezels.

Сводка рекомендуемых товаров

NXP SE050 Secure element for PCI-compliant crypto Используется в: Contactless Payment Terminal PN5120A0ET/C2EL NXP Semiconductors Используется в: Contactless Payment Terminal, Access Control Reader, Public Transport Validator, Industrial IoT Commissioning Tool, Vending Machine Payment Reader PN5120A0ET/C2J Standard production variant for consumer device Используется в: NFC Peer-to-Peer Smart Device
What protocols does the PN5120A0ET support?
The PN5120A0ET supports ISO 14443 A/B, ISO 15693, FeliCa, MIFARE Classic, MIFARE Ultralight, and NFCIP-1 peer-to-peer at 13.56 MHz. According to NXP product literature, it is a full NFC Forum-compliant frontend, meaning it covers every NFC Forum tag type (1, 2, 3, 4) as well as reader/writer and peer modes required for payment, transit, and access-control readers.
What is the supply voltage range of the PN5120A0ET?
The PN5120A0ET operates from 2.5 V to 3.6 V on its analog and digital supply pins. This makes it directly compatible with 3.3 V host microcontrollers; for 5 V hosts, a level shifter is required on the I2C, SPI, or UART lines. The internal regulator supplies the RF output stage, so no separate pump supply is needed.
Where can I buy the PN5120A0ET and what is the price?
The PN5120A0ET is in stock at major distributors including DigiKey, Mouser, and LCSC, with pricing starting at approximately $2.79 per unit at qty 1 as of 2026-10-20. Volume pricing drops to roughly $1.74 at 1000 pieces. Lead time for non-stocked variants like PN5120A0ET/C2QL is typically 8-12 weeks direct from NXP.
What is the difference between PN5120A0ET/C2J and PN5120A0ET/C2EL?
PN5120A0ET/C2J is the standard production variant, while PN5120A0ET/C2EL is a long-life-cycle / extended-supply variant aimed at industrial designs requiring guaranteed longevity. Both share the same 64-ball TFBGA footprint, same electrical specifications, and same datasheet - they differ only in NXP's longevity program status and ordering part number suffix.
How does the PN5120A0ET compare to the NXP PN532?
Both are 13.56 MHz NFC frontends from NXP with similar protocol coverage, but the PN5120A0ET is the higher-volume successor offering improved FeliCa performance and a smaller 64-ball TFBGA package compared to the older PN532's HVQFN-40. Drop-in upgrade from PN532 is NOT possible due to package difference, but designers porting firmware from PN532 will find register-level continuity, easing software reuse.
What is the best drop-in replacement for the PN5120A0ET?
For drop-in 64-ball TFBGA footprint replacement, the NXP PN5120A0ET/C2EL and PN5120A0ET/C2QL are pin-compatible variants of the same die - both source directly from the NXP product family. For cross-brand drop-in replacement, the NXP CLRC663 plus an external 3.3 V LDO is a functionally similar alternative but requires a different PCB footprint and is therefore NOT a drop-in replacement.
Is the PN5120A0ET suitable for contactless payment terminals?
Yes, the PN5120A0ET is well suited for contactless payment terminals thanks to its full NFC Forum compliance and support for ISO 14443 A/B at 13.56 MHz. Its 64-byte FIFO and hardware crypto1 acceleration offload the host processor, reducing transaction latency. Pair it with a secure element (e.g. SE050) for PCI-compliant payment applications.
What is the maximum RF output power of the PN5120A0ET?
The PN5120A0ET delivers approximately 450 mW of RF output power into a 50 ohm load under typical matching conditions, with adjustable output level via the TxLDO and CWGsP registers. Actual radiated power depends on the antenna matching network and Q factor - typical reader designs achieve 1-3 W EIRP after antenna gain.
What is the package of the PN5120A0ET?
The PN5120A0ET is housed in a 64-ball TFBGA (Thin-profile Fine-pitch Ball Grid Array) measuring 5 mm x 5 mm with 0.5 mm ball pitch. The exposed die pad underneath must be soldered to the PCB ground plane for thermal dissipation and EMC performance. Pinout and ball map are documented in the manufacturer datasheet.
Where can I download the PN5120A0ET datasheet PDF?
The PN5120A0ET datasheet is available for free download from NXP's website at https://www.nxp.com/docs/en/data-sheet/PN512.pdf. The document is approximately 137 pages covering electrical characteristics, register descriptions, antenna design, and application schematics. A copy is also available via third-party aggregators such as Alldatasheet.
Does the PN5120A0ET support host wake-up on card detection?
Yes, the PN5120A0ET supports low-power card detection modes that allow the host microcontroller to enter sleep while the frontend continuously polls for an in-field tag. When a card is detected, the IRQ pin asserts to wake the host. This makes the part well suited for battery-powered NFC readers in access control and IoT commissioning use cases.
Can the PN5120A0ET operate in peer-to-peer NFC mode?
Yes, the PN5120A0ET supports NFCIP-1 peer-to-peer mode as part of its NFC Forum compliance. In initiator mode, the part generates the 13.56 MHz RF field and modulates data onto it; in target mode, it load-modulates the field generated by another NFCIP-1 device. Peer mode is required for Android Beam-style data exchange between two NFC-enabled devices.
What is the FIFO buffer size of the PN5120A0ET?
The PN5120A0ET integrates a 64-byte FIFO buffer between the host interface and the analog front-end. This buffer holds TX data awaiting modulation and RX data awaiting host read-out. For transactions exceeding 64 bytes, the host must service the FIFO before an overflow interrupt fires.
Is the PN5120A0ET RoHS compliant?
Yes, the PN5120A0ET is RoHS compliant per NXP's product declaration, and is lead-free (Pb-free) and halogen-free. It is qualified for use in commercial and industrial products requiring EU RoHS Directive compliance. The device is not AEC-Q100 qualified - automotive applications should evaluate AEC-Q100 alternatives such as the NCF3340.
How should the PN5120A0ET antenna matching network be designed?
Antenna matching for the PN5120A0ET should target a parallel resonant LC tank at 13.56 MHz with a Q factor between 10 and 30 depending on the desired read range and bandwidth. Lower Q gives wider bandwidth tolerance for ISO 14443 vs FeliCa vs ISO 15693 (which operate at different subcarrier frequencies); higher Q extends read range. Use the NXP AN11561 application note as a starting reference design.

Справочные инженерные данные для PN5120A0ET — сравнение, рекомендации по проектированию и информация о соответствии.

Руководство по выбору

Choose PN5120A0ET/C2J (standard production) for most commercial designs where price-per-unit is the primary driver and standard NXP supply commitments are sufficient. Choose PN5120A0ET/C2EL when designing access-control, transit, or industrial readers that must remain in production for 10+ years - the /C2EL suffix enrolls the part in NXP's extended longevity program. Choose PN5120A0ET/C2QL when an even longer supply commitment is needed and you do not need a specific suffix. Choose PN5120A0ET/C2151 when authorized-channel traceability through Rochester Electronics is mandated. All four share the same 64-ball TFBGA footprint, same firmware, and same electrical characteristics - selection is driven by supply-chain and longevity requirements, not performance.

Сравнение с аналогами

Параметр Этот товар PN5120A0ET/C2EL PN5120A0ET/C2QL PN5120A0ET/C2151
Brand NXP Semiconductors NXP Semiconductors NXP Semiconductors NXP Semiconductors
Package 64-TFBGA (5x5 mm) 64-TFBGA (5x5 mm) - same 64-TFBGA (5x5 mm) - same 64-TFBGA (5x5 mm) - same
Frequency 13.56 MHz 13.56 MHz 13.56 MHz 13.56 MHz
Host Interface I2C, SPI, UART I2C, SPI, UART I2C, SPI, UART I2C, SPI, UART
Supply Voltage 2.5 V to 3.6 V 2.5 V to 3.6 V 2.5 V to 3.6 V 2.5 V to 3.6 V
Protocol Support Full NFC Forum (ISO 14443 A/B, FeliCa, MIFARE) Full NFC Forum (ISO 14443 A/B, FeliCa, MIFARE) Full NFC Forum (ISO 14443 A/B, FeliCa, MIFARE) Full NFC Forum (ISO 14443 A/B, FeliCa, MIFARE)
Ordering Variant Standard (C2J) Extended longevity (industrial) Long-life-cycle ordering code Rochester Electronics stocking variant
Lifecycle / Supply Status Active production Active - extended supply program Active - long-life ordering code Distributor stocked

Ключевые отличия

  • Full NFC Forum compliance in a single chip (против PN5120A0ET/C2EL)
  • Direct 3.3 V operation without external LDO (против PN5120A0ET/C2QL)
  • Distributor stocking at authorized channel (против PN5120A0ET/C2151)

Заметки по проектированию

Place all 100 nF decoupling capacitors within 3 mm of their respective supply pins (AVDD, DVDD, PVDD, TVDD, TVDD_PA) to suppress transients from the 13.56 MHz TX driver. Add a 10 uF bulk capacitor near the AVDD pin to filter lower-frequency noise. The exposed die pad (center balls) MUST be soldered to a continuous, unbroken ground plane on the top layer to dissipate heat and provide a low-impedance return path for the antenna currents.

Route the differential pair TX1/TX2 traces symmetrically from the IC balls to the EMC low-pass filter and antenna matching network. Keep trace lengths matched within 0.5 mm to preserve balance; imbalance causes common-mode current on the antenna that reduces read range and may cause EMC compliance failures. Keep digital lines (SDA, SCL, IRQ, RSTPD) physically separated from the antenna traces by at least 3 mm to avoid coupling.

Do not operate the PN5120A0ET without an antenna matching network - the TX outputs are designed for a 50 ohm reference impedance and require an LC tank tuned to 13.56 MHz. Avoid using long wires between the IC and antenna; total trace + loop length should be less than one wavelength (about 22 m at 13.56 MHz in vacuum) but in practice under 1 m is recommended to avoid radiated emissions above regulatory limits.

Estimated: At continuous full RF output (~450 mW into 50 ohm) with VDD = 3.3 V, the PN5120A0ET dissipates roughly 1 W in the TX driver stage. With the exposed pad soldered to a 1-square-inch copper ground plane on a 4-layer FR-4 PCB, theta_JA is approximately 40 C/W, yielding a junction temperature rise of 40 C above ambient. Adequate for commercial 85 C operation; for industrial 85 C environments at elevated ambient, increase copper area or add thermal vias.

The PN5120A0ET uses a 27.12 MHz crystal oscillator (2x carrier) referenced from OSCIN/OSCOUT. Place the crystal within 5 mm of these pins with short, symmetric traces and guard it with a ground ring. Use a crystal with ESR under 60 ohm and load capacitance matching the datasheet-specified value (typically 15 pF) for clean carrier generation and reliable start-up across the full 2.5 V to 3.6 V supply range.

Информация о соответствии

RoHS
Compliant
REACH
Compliant
AEC-Q100
Not Applicable
Без свинца
Yes
Без галогенов
Yes
Конфликтные минералы
Compliant

RoHS compliant per NXP product declaration; not AEC-Q100 qualified - automotive applications should evaluate NCF3340 (AEC-Q100) or similar.

Данные проверены: 2026-10-20 — данные проверены и курируются командой компонентной инженерии XAIPART

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Связанные компоненты & термины

NXP Semiconductors PN5120A0ET PN5120A0ET/C2J PN5120A0ET/C2EL PN5120A0ET/C2QL PN5120A0ET/C2151 NFC frontend RFID reader 13.56 MHz ISO 14443 ISO 15693 FeliCa MIFARE NFCIP-1 NFC Forum TFBGA I2C SPI UART contactless payment access control EMVCo PCI RoHS TFBGA-64
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