10AS057K2F35I2LG vs 10AS057K2F35I2SG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AS057K2F35I2LG sa pamamagitan ng Intel at 10AS057K2F35I2SG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 10AS057K2F35I2LG | 10AS057K2F35I2SG |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Arria 10 SX SoC FPGA | Arria 10 SX SoC FPGA |
| Logic Elements | 570,000 | 570K |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 1.5 GHz | — |
| Process Technology | 20 nm TSMC | — |
| Packhaging | 1152-pin FC-FBGA (F35), 35 x 35 mm | 1152-ball FC-FBGA (F35), 35x35 mm |
| Package Code | F35 / 1152-BGA | — |
| Ball Pitch | 1.0 mm | — |
| Temperature Grade | Industrial (-40C to +100C ambient) | — |
| Speed Grade | -I2 | -2 |
| Supply Voltage (Core) | 0.9 V | — |
| Connectivity | SPI, UART/USART, EBI/EMI, USB, GbE, PCIe | — |
| Memory Interface | DDR3, DDR4, LPDDR3 (via HPS/FPGA controllers) | — |
| Uri ng Pagpapasok | Surface Mount (FC-FBGA) | Surface Mount (BGA) |
| Tindminan RoHS | Compliant | Compliant (lead-free finish) |
| Processor Core | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Core Frequency | — | 1.5 GHz |
| Temperature na Operasyon | — | -40C to +100C (Industrial) |
| User I/O Count | — | 396 (per Heisener parametric data) |
| Process Node | — | 20 nm TSMC |
| Transceivers | — | [DATA_NEEDED: transceiver count and max data rate] |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Embedded Memory | — | [DATA_NEEDED: M20K / MLAB bit count] |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, SPI, I2C, NAND/NOR flash controllers, SD/MMC |
| Memory Interfaces | — | DDR3/DDR4/LPDDR3 hard controllers (Arria 10 HPS) |
| Configuration | — | FPGA + HPS independent / coordinated boot |
| Level ng MSL | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |