10AS057K3F35E2SG vs 10AS057K2F35I2SG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AS057K3F35E2SG sa pamamagitan ng Intel at 10AS057K2F35I2SG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 10AS057K3F35E2SG | 10AS057K2F35I2SG |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Arria 10 SX SoC FPGA | Arria 10 SX SoC FPGA |
| Logic Elements | 570,000 | 570K |
| Process Technology | 20 nm | — |
| Hard Processor Subsystem | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Core Voltage | 0.9 V | — |
| Packhaging | 1152-pin FC-FBGA (35x35 mm) | 1152-ball FC-FBGA (F35), 35x35 mm |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Temperature na Operasyon | 0 C to +85 C (industrial) | -40C to +100C (Industrial) |
| Lead-Free / RoHS | Yes / Compliant | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |
| Core Speed | up to 1.5 GHz | — |
| Configuration Memory | [DATA_NEEDED: bit-width / type] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | [DATA_NEEDED: DSP block count] |
| Embedded Memory | [DATA_NEEDED: M20K block count / total] | [DATA_NEEDED: M20K / MLAB bit count] |
| Transceivers | [DATA_NEEDED: transceiver count / rate] | [DATA_NEEDED: transceiver count and max data rate] |
| User I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| Processor Core | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Core Frequency | — | 1.5 GHz |
| Speed Grade | — | -2 |
| User I/O Count | — | 396 (per Heisener parametric data) |
| Process Node | — | 20 nm TSMC |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, SPI, I2C, NAND/NOR flash controllers, SD/MMC |
| Memory Interfaces | — | DDR3/DDR4/LPDDR3 hard controllers (Arria 10 HPS) |
| Configuration | — | FPGA + HPS independent / coordinated boot |
| Tindminan RoHS | — | Compliant (lead-free finish) |