10AX090S2F45E1SG vs 10AX090S3F45E2SG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AX090S2F45E1SG sa pamamagitan ng Intel at 10AX090S3F45E2SG sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
10AX090S3F45E2SG - Arria 10 GX FPGA, 900K LE, 1932-FCBGA | Intel / Altera
10AX090S3F45E2SG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 10AX090S2F45E1SG | 10AX090S3F45E2SG |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Arria 10 GX | Arria 10 GX |
| Device | 10AX090 | — |
| Logic Elements (LE) | 900,000 | 900,000 |
| Embedded Memory | 59,234,304 bits | — |
| DSP Blocks | 1,518 (variable-precision, hard floating-point) | Variable-precision, with hardened single-precision FP |
| Transceivers | 24 channels | — |
| Max Transceiver Data Rate | 12.5 Gbps | — |
| Packhaging | 1932-ball FCBGA | 1932-BBGA, FCBGA (F45, 45 mm) |
| Package Code | F45 | — |
| Speed Grade | -E1 (fastest) | S3 |
| Device Variant | -S2 (lower-power core) | 10AX090 |
| Operating Temperature Grade | Extended | — |
| Process Node | 20 nm TSMC | 20 nm TSMC |
| Hard PCIe Gen3 Blocks | Yes, up to 96 lanes | — |
| Configuration Method | Active serial (AS), Passive serial (PS), JTAG | — |
| Tindminan RoHS | Compliant | Compliant |
| Embedded Memory Bits | — | 59,234,304 bits |
| User I/O Count | — | 624 |
| Transceiver Protocol | — | GX (up to 12.5 Gbps) |
| PCI Express Hard IP | — | Gen3 x8 |
| Memory Controller | — | Hard DDR3/DDR4/QDRII+/RLDRAM3 controller |
| Configuration | — | Active/passive serial, JTAG |
| Temperature na Operasyon | — | Industrial (E2 suffix: -40C to +100C) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |