10AX090S2F45I2LG vs 10AX090S3F45I2LG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AX090S2F45I2LG sa pamamagitan ng Intel at 10AX090S3F45I2LG sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
10AX090S3F45I2LG - Arria 10 GX 900K LE FPGA, 1932-FCBGA | Intel / Altera
10AX090S3F45I2LG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 10AX090S2F45I2LG | 10AX090S3F45I2LG |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Arria 10 GX | — |
| Device Model | 10AX090 | — |
| Logic Elements | 900000 | 900,000 |
| Embedded Memory Bits | 59234304 | — |
| Number of User I/Os | 624 | — |
| Package Type | 1932-BBGA, FCBGA | — |
| Operating Voltage (Core) | 0.9 V | — |
| Process Technology | 20 nm | 20nm Tri-Gate |
| Operating Temperature Grade | Industrial | — |
| Temperature Range (I2 suffix) | -40C to +100C | — |
| Speed Grade | 2 | -I2 (industrial) |
| Lead Finish | Lead-free (LG suffix, RoHS compliant) | — |
| Tindminan RoHS | Compliant | Compliant |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Terminal Form | Ball | — |
| Package Code | BGA, FCBGA | — |
| Package Shape | Square | — |
| Series | — | Arria 10 GX |
| Embedded Memory | — | 59,234,304 bits (1,830 M20K blocks) |
| DSP Blocks | — | 759 (variable-precision, hardened 27x27 multipliers) |
| User I/O Count | — | 624 |
| Transceivers | — | Up to 24.0 Gbps (GX family) |
| PCIe Hard IP | — | PCI Express Gen3 x8 (hardened) |
| Memory Interface Hard IP | — | DDR4 / LPDDR4 / DDR3 up to 2666 Mbps |
| Packhaging | — | 1932-ball FCBGA (F45, 45x45 mm) |
| Temperature na Operasyon | — | -40C to +100C (industrial Tj) |
| Configuration | — | Partial reconfiguration, AES-256 bitstream encryption |
| Supply Voltage (Core) | — | 0.85 V (nominal VCORE) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |