10AX115N3F40E2LG vs 10AX115R2F40E1SG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AX115N3F40E2LG sa pamamagitan ng Altera at 10AX115R2F40E1SG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
10AX115N3F40E2LG - Arria 10 GX FPGA 1150K LE | Altera | F40 FCBGA
10AX115N3F40E2LG ✓ NakahandaIntel
10AX115R2F40E1SG - Arria 10 GX FPGA, 1150K LE, 1517-FCBGA | Intel
10AX115R2F40E1SG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 10AX115N3F40E2LG | 10AX115R2F40E1SG |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Arria 10 GX | Arria 10 GX |
| Family | 10AX115 | Arria 10 |
| Logic Elements (LE) | 1,150,000 | 1,150,000 |
| Embedded Memory Bits | 68,857,856 | — |
| Number of I/O | 600 | 342 |
| Packhaging | 1517-BBGA, FCBGA (F40, 40 mm, 1.0 mm pitch) | 1517-ball FCBGA (F40) 40x40 mm |
| Speed Grade | -2 | -2 |
| Core Performance Grade | N (nominal) | — |
| Process Technology | 20 nm | 20 nm TSMC tri-gate (FinFET) |
| Transceivers (GXT, up to 17.4 Gbps) | up to 24 per device family | — |
| Transceivers (GX, up to 12.5 Gbps) | up to 48 per device family | — |
| DSP Blocks (18x19 Multipliers) | 1,518 | — |
| PCIe Hard IP | Gen3 x4 / x8 hard blocks | — |
| Temperature na Operasyon | -40C to +100C (junction, industrial envelope) | — |
| Lead-Free Finish | Yes (LG suffix) | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Embedded Memory (bits) | — | 68,857,856 |
| DSP Blocks | — | 1,518 (variable-precision 20x19) |
| Transceivers | — | GX transceivers up to 14.2 Gbps |
| Hard Memory Controllers | — | Yes (DDR4, DDR3, LPDDR3, QDR IV) |
| Hard PCIe Block | — | PCIe Gen3 x8 |
| Temperature Grade | — | Extended (-E1) |
| Tindminan RoHS | — | Compliant |
| Lead Free | — | Yes |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Configuration | — | SRAM-based, supports partial reconfiguration |