10AX115N4F40E3LG vs 10AX115N4F40I3SG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AX115N4F40E3LG sa pamamagitan ng Intel at 10AX115N4F40I3SG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
10AX115N4F40I3SG - Arria 10 GX 1150K LE FPGA | Intel | 1517-FCBGA
10AX115N4F40I3SG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 10AX115N4F40E3LG | 10AX115N4F40I3SG |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Product Type | FPGA - Field Programmable Gate Array | — |
| Family | Arria 10 GX | Arria 10 GX |
| Logic Elements (LE) | 1,150,000 | 1,150,000 |
| Adaptive Logic Modules (ALM) | 427,200 | [DATA_NEEDED: ALM count] |
| Embedded Memory Bits | 68,857,856 (approx. 53 Mb) | 68,857,856 |
| M20K Memory Blocks | 2,738 | — |
| MLAB Memory (Kb) | 12,962 | — |
| DSP Blocks | 600 (variable-precision) | [DATA_NEEDED: DSP block count] |
| 18x19 Multipliers | 1,536 | — |
| Maximum User I/O | 624 | 600 |
| Transceivers | 24 (up to 14.1 Gbps) | — |
| Transceiver Data Rate | 1.0 to 14.1 Gbps | — |
| PCIe Hard IP | Up to Gen3 x8 | — |
| Process Technology | TSMC 20 nm | — |
| Core Voltage | 0.85 V / 0.9 V typical | — |
| Packhaging | 1517-BBGA, FCBGA (40 x 40 mm) | 1517-BBGA, FCBGA (F40), 40 x 40 mm, 1.00 mm pitch |
| Temperature na Operasyon | -40C to +100C (extended) | -40C to +100C (Industrial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Tindminan RoHS | Compliant | Compliant |
| Configuration Method | Serial / JTAG / Active Serial (AS) | — |
| Lead-Free | Yes | — |
| Transceiver Count | — | [DATA_NEEDED: transceiver count] |
| Maximum Transceiver Data Rate | — | 17.4 Gbps |
| Process Node | — | 20 nm |
| Supply Voltage (Core) | — | [DATA_NEEDED: VCC core voltage] |
| Configuration | — | Serial, Parallel, and Avalon-ST supported |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |
| Hardened IP | — | PCIe Gen3, 100G Ethernet MAC (per Quartus IP library) |
| Device Family Position | — | Mid-range 20 nm transceiver FPGA |