10AX115R2F40E2SG vs 10AX115R2F40E1SG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AX115R2F40E2SG sa pamamagitan ng Intel at 10AX115R2F40E1SG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
10AX115R2F40E1SG - Arria 10 GX FPGA, 1150K LE, 1517-FCBGA | Intel
10AX115R2F40E1SG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 10AX115R2F40E2SG | 10AX115R2F40E1SG |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Arria 10 GX | Arria 10 |
| Logic Elements (LE) | 1,150,000 | 1,150,000 |
| Adaptive Logic Modules (ALM) | 427,200 | — |
| Embedded Memory Bits | 68,857,856 | — |
| M20K Memory Blocks | 2,128 | — |
| MLAB Memory Bits | 8,812,800 | — |
| Variable-Precision DSP Blocks | 1,518 | — |
| 18 x 19 Multipliers | 3,036 | — |
| PLLs | 16 | — |
| User I/O Pins | 342 | — |
| Transceiver Count | 48 (max 96 for the family) | — |
| Transceiver Data Rate | up to 17.4 Gbps (chip-to-chip) | — |
| Hard Memory Controllers | Yes | Yes (DDR4, DDR3, LPDDR3, QDR IV) |
| PCIe Hard IP | Gen3 x1/x2/x4/x8 | — |
| Process Technology | 20 nm TSMC | 20 nm TSMC tri-gate (FinFET) |
| Speed Grade | -2 (E2, mid) | -2 |
| Temperature na Operasyon | 0C to +100C (commercial) | — |
| Packhaging | 1517-ball FCBGA, 40 x 40 mm | 1517-ball FCBGA (F40) 40x40 mm |
| Uri ng Pagpapasok | Surface Mount (flip-chip BGA) | Surface Mount |
| RoHS | Compliant | — |
| Series | — | Arria 10 GX |
| Embedded Memory (bits) | — | 68,857,856 |
| Number of I/O | — | 342 |
| DSP Blocks | — | 1,518 (variable-precision 20x19) |
| Transceivers | — | GX transceivers up to 14.2 Gbps |
| Hard PCIe Block | — | PCIe Gen3 x8 |
| Temperature Grade | — | Extended (-E1) |
| Tindminan RoHS | — | Compliant |
| Lead Free | — | Yes |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Configuration | — | SRAM-based, supports partial reconfiguration |