10AX115R2F40I2LG vs 10AX115R2F40E1SG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AX115R2F40I2LG sa pamamagitan ng Intel at 10AX115R2F40E1SG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
10AX115R2F40E1SG - Arria 10 GX FPGA, 1150K LE, 1517-FCBGA | Intel
10AX115R2F40E1SG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 10AX115R2F40I2LG | 10AX115R2F40E1SG |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Arria 10 GX | Arria 10 GX |
| Family | Intel Arria 10 | Arria 10 |
| Logic Elements (LE) | 1,150,000 | 1,150,000 |
| Adaptive Logic Modules (ALM) | [DATA_NEEDED: ALM count] | — |
| Embedded Memory (M20K blocks) | [DATA_NEEDED: M20K block count] | — |
| Embedded Memory Bits | 68,857,856 bits (68.86 Mbit) | — |
| User I/O Pins | 342 | — |
| Transceiver Channels | 24 (up to 28.05 Gbps) | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | 1,518 (variable-precision 20x19) |
| PCI Express Hard IP | Yes (Gen3 x8 capable) | — |
| Process Node | 20 nm TSMC | — |
| Core Voltage | 0.9 V | — |
| Packhaging | 1517-ball FC-FBGA | 1517-ball FCBGA (F40) 40x40 mm |
| Package Code | F40 (FCFBGA-1517) | — |
| Operating Temperature Grade | Industrial (-40C to +100C) | — |
| Tindminan RoHS | Compliant | Compliant |
| Lead-Free | Yes | — |
| Embedded Memory (bits) | — | 68,857,856 |
| Number of I/O | — | 342 |
| Transceivers | — | GX transceivers up to 14.2 Gbps |
| Hard Memory Controllers | — | Yes (DDR4, DDR3, LPDDR3, QDR IV) |
| Hard PCIe Block | — | PCIe Gen3 x8 |
| Process Technology | — | 20 nm TSMC tri-gate (FinFET) |
| Speed Grade | — | -2 |
| Temperature Grade | — | Extended (-E1) |
| Uri ng Pagpapasok | — | Surface Mount |
| Lead Free | — | Yes |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Configuration | — | SRAM-based, supports partial reconfiguration |