10AX115U2F45E2LG vs 10AX115U3F45E2SG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AX115U2F45E2LG sa pamamagitan ng Intel at 10AX115U3F45E2SG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
10AX115U2F45E2LG - Arria 10 GX 1.15M LE FPGA | Intel F45 FCBGA-1932
10AX115U2F45E2LG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 10AX115U2F45E2LG | 10AX115U3F45E2SG |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Arria 10 GX | — |
| Family | Arria 10 | Arria 10 GX |
| Logic Elements (LE) | 1,150,000 | 1,150,000 |
| Adaptive Logic Modules (ALM) | 427,200 | 427,200 |
| Embedded Memory | 52.99 Mbit | — |
| Number of User I/O | 480 | — |
| Packhaging | 1932-BBGA, FCBGA (F45, 45 mm) | 1932-ball FCBGA (F45, 45×45 mm, 1.0 mm pitch) |
| Process Technology | 20 nm | — |
| Core Voltage | 0.9 V | — |
| Transceiver Data Rate | up to 28.05 Gbps (per Arria 10 GX family) | — |
| Number of Terminals | 1932 | — |
| Terminal Form | Ball (BGA) | — |
| Package Shape | Square | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Operating Temperature Grade | Extended (per -E suffix) | — |
| Tindminan RoHS | Compliant | — |
| Embedded Memory Bits | — | 68,857,856 (≈ 52.99 Mbit) |
| Number of Transceivers | — | [DATA_NEEDED: per-die transceiver count, F45 package variant] |
| Maximum Transceiver Data Rate | — | 17.4 Gbps |
| DSP Blocks | — | Variable-precision, hardened floating-point |
| Hard Memory Controllers | — | 2 (DDR4/DDR3/QDRII+/RLDRAM3) |
| Hard PCIe Gen3 IP Blocks | — | 2 × PCIe Gen3 (x8/x4/x2/x1) |
| Process Node | — | 20 nm Tri-Gate (Intel) |
| Speed Grade | — | -2 (E2 commercial/extended) |
| Temperature na Operasyon | — | Industrial (junction -40 °C to +100 °C) – device grade U |
| Supply Voltage Core | — | [DATA_NEEDED: VCC/VCCP core voltage] |
| Configuration Method | — | FPGA configuration via serial/parallel flash, JTAG |
| RoHS Compliance | — | Compliant |
| Level ng MSL | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |