10AX115U3F45I2LG vs 10AX115U3F45E2SG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AX115U3F45I2LG sa pamamagitan ng Altera at 10AX115U3F45E2SG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
10AX115U3F45I2LG - Arria 10 GX FPGA, 1.15M LE | Intel | 1932-BGA
10AX115U3F45I2LG ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 10AX115U3F45I2LG | 10AX115U3F45E2SG |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Arria 10 GX | Arria 10 GX |
| Logic Elements | 1,150,000 LE | — |
| Adaptive Logic Modules (ALMs) | 427,200 ALM | — |
| Embedded Memory | 68,857,856 bit (52.99 Mbit) | — |
| DSP Blocks | 480 | Variable-precision, hardened floating-point |
| Transceivers | 24 (up to 12.5 Gbps, U3 speed grade) | — |
| Process Technology | 20nm | — |
| Packhaging | 1932-BBGA, FCBGA (F45) 45mm | 1932-ball FCBGA (F45, 45×45 mm, 1.0 mm pitch) |
| Temperature na Operasyon | -40C to +100C (Industrial) | Industrial (junction -40 °C to +100 °C) – device grade U |
| Uri ng Pagpapasok | Surface Mount (BGA) | — |
| Packaging | Tray | — |
| Configuration Memory | SRAM-based (volatile) | — |
| Hard Memory Controllers | Yes | 2 (DDR4/DDR3/QDRII+/RLDRAM3) |
| Hard PCIe Blocks | Yes (Gen3) | — |
| Tindminan RoHS | Compliant | — |
| Logic Elements (LE) | — | 1,150,000 |
| Adaptive Logic Modules (ALM) | — | 427,200 |
| Embedded Memory Bits | — | 68,857,856 (≈ 52.99 Mbit) |
| Number of Transceivers | — | [DATA_NEEDED: per-die transceiver count, F45 package variant] |
| Maximum Transceiver Data Rate | — | 17.4 Gbps |
| Hard PCIe Gen3 IP Blocks | — | 2 × PCIe Gen3 (x8/x4/x2/x1) |
| Process Node | — | 20 nm Tri-Gate (Intel) |
| Speed Grade | — | -2 (E2 commercial/extended) |
| Supply Voltage Core | — | [DATA_NEEDED: VCC/VCCP core voltage] |
| Configuration Method | — | FPGA configuration via serial/parallel flash, JTAG |
| RoHS Compliance | — | Compliant |
| Level ng MSL | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |