10CL040YF484I7G vs 10CL040YU484I7G Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10CL040YF484I7G sa pamamagitan ng Intel at 10CL040YU484I7G sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 10CL040YF484I7G | 10CL040YU484I7G |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Cyclone 10 LP | — |
| Family | 10CL040 (Cyclone 10 LP) | Cyclone 10 LP |
| Logic Elements (LE) | 39,600 | 39,600 |
| Embedded Memory (bits) | 1,161,216 | — |
| Embedded Memory Blocks | M9K (9 Kbit each) | — |
| Maximum User I/O | 325 (package-limited; silicon max 426) | 325 |
| Number of I/O Banks | 8 | — |
| Packhaging | 484-FBGA (FineLine BGA, 23 x 23 mm, 1.0 mm pitch) | 484-pin UBGA (Ultra FineLine BGA) |
| Process Technology | TSMC 60 nm low-power | TSMC 60 nm low-power |
| Core Voltage | 1.0 V (nominal) | 1.0 V to 1.2 V |
| Multipliers (18x18) | Up to 148 | — |
| PLLs | Up to 4 | — |
| Hard PCIe IP | PCIe Gen1 x1 (hardened) | — |
| LVDS Support | Per-pin hardened LVDS receivers | — |
| I/O Voltage Standards | 1.0 / 1.2 / 1.5 / 1.8 / 2.5 / 3.3 V | — |
| Configuration Modes | Serial (EPCS/AS), JTAG, Parallel | — |
| Temperature Grade | Industrial (-40C to +100C junction) | — |
| Speed Grade | I7 (industrial, fastest) | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | Compliant | Compliant |
| Configurable Logic Blocks (CLB) | — | 2,475 |
| Embedded Memory | — | 1,161,216 bits (M9K blocks) |
| Embedded 18x18 Multipliers | — | 66 |
| General-Purpose PLLs | — | 4 |
| Temperature na Operasyon | — | -40 C to +100 C (Industrial) |
| Ball Pitch | — | 0.8 mm |
| Configuration Mode | — | JTAG / AS / PS |
| Supply Form | — | Tray |