2EDL8124GXUMA1 vs 2ED21844S06JXUMA1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 2EDL8124GXUMA1 sa pamamagitan ng Infineon at 2ED21844S06JXUMA1 sa pamamagitan ng Infineon. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Infineon
2EDL8124GXUMA1 - 120V Boot 4A Junction-isolated Gate Driver | Infineon
2EDL8124GXUMA1 ✓ NakahandaInfineon
2ED21844S06JXUMA1 - 650V Half-Bridge Gate Driver 2.5A | Infineon
2ED21844S06JXUMA1 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 2EDL8124GXUMA1 | 2ED21844S06JXUMA1 |
|---|---|---|
| Brand | Infineon | Infineon |
| Kategorya | Power MOSFET Drivers | Power MOSFET Drivers |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Driver Configuration | Half-bridge (high-side + low-side) | Half-Bridge |
| Input Type | Non-inverting, TTL-compatible with hysteresis | Non-Inverting |
| Number of Drivers | 2 | 2 (high-side + low-side) |
| Peak Source Current | 3 A | — |
| Peak Sink Current | 4 A | — |
| Bootstrap Supply (VBS) Maximum | 120 V | — |
| VCC Supply Range | [DATA_NEEDED: VCC min/max typical range] | — |
| Isolation Type | Junction isolation (JI) | — |
| Bootstrap Diode | Integrated | Integrated |
| Propagation Delay (typical) | < 50 ns | — |
| Delay Matching Between Channels | [DATA_NEEDED: delay matching spec in ns] | — |
| UVLO | Present on VCC and VBS | — |
| Hanay ng Temperature na Operasyon | [DATA_NEEDED: operating temperature range in C] | -40 C to +125 C |
| Packhaging | PG-VDSON-8-4 (4 mm x 4 mm) with exposed pad | PG-DSO-14-49 (DSO-14) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL level] |
| Tindminan RoHS | Compliant | Compliant |
| Lead-Free | Yes | — |
| Blocking Voltage (Voffset) | — | 650 V |
| Output Current (Source/Sink) | — | 2.5 A typical |
| Supply Voltage (VCC) | — | 10 V to 20 V [DATA_NEEDED: exact range] |
| Propagation Delay (Typ.) | — | 200 ns [DATA_NEEDED: matching value] |
| Input Logic Compatibility | — | TTL/CMOS 3.3 V and 5 V |
| Undervoltage Lockout (UVLO) | — | Yes, both HS and LS rails |
| Shutdown Pin | — | Yes |
| Negative VS Transient Immunity | — | -100 V typical |