5CSEBA2U23C7N vs 5CSEBA2U23A7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA2U23C7N sa pamamagitan ng Intel at 5CSEBA2U23A7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 5CSEBA2U23C7N | 5CSEBA2U23A7N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 25K | 25,000 LE |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 800 MHz (application grade) | 700 MHz |
| Packhaging | 672-UBGA (23x23 mm) | 672-UBGA (23x23 mm) |
| User I/O | 188 | 188 |
| Process Technology | TSMC 28 nm low-power | 28 nm low-power |
| DSP Blocks | Variable-precision (count [DATA_NEEDED: DSP block count]) | Variable-precision DSP (count [DATA_NEEDED: exact count]) |
| Embedded Memory | M10K RAM blocks (total bits [DATA_NEEDED: M10K total bits]) | M10K blocks (count [DATA_NEEDED: exact M10K/M20K count]) |
| HPS Memory Interface | DDR3 / DDR3L / LPDDR2 controller | — |
| HPS Peripherals | Gigabit Ethernet MAC, USB 2.0 OTG, NAND, SD/eMMC | — |
| High-Speed Transceivers | Present (channel count [DATA_NEEDED: transceiver count]) | — |
| Temperature na Operasyon | [DATA_NEEDED: Tj/Ta commercial range] | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Tindminan RoHS | Compliant | Compliant (per ampheo listing) |
| MPN Code | — | 5CSEBA2U23A7N (Cyclone V SE A2, U23 package) |
| Hard Processor System (HPS) | — | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| Speed Grade | — | 7 |
| Temperature Grade | — | A (Commercial, 0C to +85C) [DATA_NEEDED: exact junction range] |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Operating Voltage (Core) | — | 1.1 V (typical FPGA core, multi-rail HPS) |
| Configuration Scheme | — | HPS-boot of FPGA fabric via configuration QSPI |
| PLLs | — | Fractional PLLs (count [DATA_NEEDED: exact PLL count]) |