5CSEBA4U19C8SN vs 5CSEBA4U19I7SN Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA4U19C8SN sa pamamagitan ng Intel at 5CSEBA4U19I7SN sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
5CSEBA4U19C8SN - Cyclone V SE SoC FPGA, 40K LE, ARM Cortex-A9 | Intel
5CSEBA4U19C8SN ✓ NakahandaIntel
5CSEBA4U19I7SN - Cyclone V SE SoC FPGA, 40K LE, ARM Cortex-A9 | Intel
5CSEBA4U19I7SN ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSEBA4U19C8SN | 5CSEBA4U19I7SN |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Cyclone V SE SoC FPGA | — |
| Logic Elements | 40,000 | 40,000 |
| Hard Processor System | Single ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum User I/Os | 161 | — |
| Operating Frequency (HPS) | 600 MHz | — |
| Supply Voltage (Core) | 1.1 V | 1.1 V (typical) |
| Process Technology | 28 nm low-power | — |
| Packhaging | 484-UBGA (19x19 mm) | 484-pin UBG A (19x19 mm) |
| Speed Grade | -8 (commercial) | — |
| Temperature Range | 0C to +85C (commercial) | — |
| Number of Pins/Balls | 484 | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Series | Cyclone V | Cyclone V SE SoC FPGA |
| Tindminan RoHS | Compliant | Compliant |
| Lead-Free | Yes | — |
| Device Family | — | Cyclone V |
| Hard Processor System (HPS) | — | Single ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 800 MHz |
| Temperature na Operasyon | — | -40C to +100C (Industrial) |
| Process Node | — | 28 nm low-power |
| I/O Standards Supported | — | LVTTL, LVCMOS, LVDS, SSTL, HSTL (Cyclone V I/O family) |
| Embedded Memory | — | [DATA_NEEDED: total Kbits of M9K blocks] |
| 18x18 Hardware Multipliers | — | [DATA_NEEDED: count] |
| PLLs | — | [DATA_NEEDED: count] |
| Transceivers | — | Not applicable (SE family, transceiver-less) |
| PCI Express Hard IP | — | Gen1 capable (rootport/endpoint) |
| DDR Memory Support | — | DDR2/DDR3/LPDDR2 via HPS and FPGA fabric |