5CSEBA5U19C8SN vs 5CSEBA4U19I7SN Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA5U19C8SN sa pamamagitan ng Intel at 5CSEBA4U19I7SN sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
5CSEBA5U19C8SN - Cyclone V SE SoC FPGA, 85K LE, ARM Cortex-A9 | Intel
5CSEBA5U19C8SN ✓ NakahandaIntel
5CSEBA4U19I7SN - Cyclone V SE SoC FPGA, 40K LE, ARM Cortex-A9 | Intel
5CSEBA4U19I7SN ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSEBA5U19C8SN | 5CSEBA4U19I7SN |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Cyclone V SE SoC FPGA | — |
| Device Variant | 5CSEBA5 (U19 package) | — |
| Logic Elements | 85 K | 40,000 |
| Hard Processor System | Single-core ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 600 MHz | 800 MHz |
| Process Technology | TSMC 28 nm low-power | — |
| Embedded Memory | [DATA_NEEDED: total Kbits] | [DATA_NEEDED: total Kbits of M9K blocks] |
| DSP Blocks | [DATA_NEEDED: variable-precision DSP count] | — |
| Hard Memory Controller | DDR2 / DDR3 / LPDDR2 | — |
| Core Voltage | 1.1 V | — |
| Packhaging | 484-pin UFBGA (U19, 19x19 mm) | 484-pin UBG A (19x19 mm) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Temperature na Operasyon | 0C to +85C (commercial) | -40C to +100C (Industrial) |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Tindminan RoHS | Compliant | Compliant |
| Lead-Free | Yes | — |
| Configuration Method | Serial / Parallel flash, JTAG | — |
| Series | — | Cyclone V SE SoC FPGA |
| Device Family | — | Cyclone V |
| Hard Processor System (HPS) | — | Single ARM Cortex-A9 MPCore with CoreSight |
| Process Node | — | 28 nm low-power |
| Supply Voltage (Core) | — | 1.1 V (typical) |
| I/O Standards Supported | — | LVTTL, LVCMOS, LVDS, SSTL, HSTL (Cyclone V I/O family) |
| 18x18 Hardware Multipliers | — | [DATA_NEEDED: count] |
| PLLs | — | [DATA_NEEDED: count] |
| Transceivers | — | Not applicable (SE family, transceiver-less) |
| PCI Express Hard IP | — | Gen1 capable (rootport/endpoint) |
| DDR Memory Support | — | DDR2/DDR3/LPDDR2 via HPS and FPGA fabric |