5CSEBA5U19I7LN vs 5CSEBA5U19C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA5U19I7LN sa pamamagitan ng Intel at 5CSEBA5U19C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
5CSEBA5U19I7LN - Cyclone V SE SoC FPGA, 85K LE, 925MHz, U19 | Intel
5CSEBA5U19I7LN ✓ NakahandaIntel
5CSEBA5U19C7N - Cyclone V SE SoC FPGA 85K LE Dual A9 800MHz | Altera
5CSEBA5U19C7N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSEBA5U19I7LN | 5CSEBA5U19C7N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 85 K | 85,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | 925 MHz | 800 MHz per core |
| Packhaging | 484-UBGA (U19), 19x19 mm | 484-UBGA (UBGAmobile, 19x19 mm) |
| Hanay ng Temperature na Operasyon | -40C to +100C (Industrial) | — |
| Speed Grade | I7 | -7 (standard) |
| Embedded Memory | 4.45 Mbits | M10K + MLAB blocks, ~4,450 Kbits total |
| DSP Blocks | 156 | Variable-precision, 18x18 / 27x27 multipliers |
| User I/O Pins | 364 | — |
| I/O Banks | 8 | — |
| Transceivers | Up to 3.125 Gbps | — |
| Hard Memory Controller | DDR3 with ECC support | — |
| Hard PCIe | PCIe Gen2 x4 | — |
| Hard Ethernet MAC | Gigabit Ethernet | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Level ng MSL | [DATA_NEEDED: MSL rating] | 3 (per JEDEC J-STD-020, reflow 260C) |
| Tindminan RoHS | Compliant | — |
| Temperature na Operasyon | — | 0C to +85C (commercial, junction) |
| Process Node | — | 28 nm low-power (TSMC) |
| Supply Voltage (Core) | — | 1.1 V typical |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, NAND, DDR3, SPI, QSPI, I2C, UART |
| RoHS / Pb-free | — | Yes |
| Configuration Memory | — | External (active serial via HPS or FPGA) |
| Block Pins (User I/O) | — | Approximately 66 user I/O pins |