5CSEBA6U19C7N vs 5CSEBA5U19C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA6U19C7N sa pamamagitan ng Intel at 5CSEBA5U19C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
5CSEBA6U19C7N - Cyclone V SE SoC FPGA, 110K LE, Dual ARM Cortex-A9 | Intel
5CSEBA6U19C7N ✓ NakahandaIntel
5CSEBA5U19C7N - Cyclone V SE SoC FPGA 85K LE Dual A9 800MHz | Altera
5CSEBA5U19C7N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSEBA6U19C7N | 5CSEBA5U19C7N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Product Type | SoC FPGA (System-on-Chip) | — |
| Series | Cyclone V SE | — |
| Family | Cyclone V | Cyclone V SE SoC FPGA |
| Logic Elements | 110,000 | 85,000 |
| Processor | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 925 MHz | 800 MHz per core |
| FPGA Maximum Frequency | 800 MHz | — |
| Process Technology | 28 nm low-power | — |
| Packhaging | 484-UBGA (U19) 19x19 mm | 484-UBGA (UBGAmobile, 19x19 mm) |
| Bilang ng Pin | 484 | — |
| User I/O | 66 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Operating Temperature Grade | Industrial / Commercial | — |
| Memory Interface | DDR3 with ECC (via HPS) | — |
| Tindminan RoHS | Compliant | — |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Temperature na Operasyon | — | 0C to +85C (commercial, junction) |
| Speed Grade | — | -7 (standard) |
| Process Node | — | 28 nm low-power (TSMC) |
| Supply Voltage (Core) | — | 1.1 V typical |
| DSP Blocks | — | Variable-precision, 18x18 / 27x27 multipliers |
| Embedded Memory | — | M10K + MLAB blocks, ~4,450 Kbits total |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, NAND, DDR3, SPI, QSPI, I2C, UART |
| RoHS / Pb-free | — | Yes |
| Configuration Memory | — | External (active serial via HPS or FPGA) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020, reflow 260C) |
| Block Pins (User I/O) | — | Approximately 66 user I/O pins |