5M160ZE64A5N vs 5M160ZE64I5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M160ZE64A5N sa pamamagitan ng Altera at 5M160ZE64I5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
5M160ZE64A5N - 128 Macro Cell MAX V CPLD, 118.3MHz, 64-EQFP | Altera
5M160ZE64A5N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5M160ZE64A5N | 5M160ZE64I5N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX V | — |
| Device | 5M160ZE64A5N | — |
| Macro Cells | 128 | — |
| Logic Elements | 160 | — |
| User I/O Pins | 54 | — |
| Maximum Operating Frequency | 118.3 MHz | — |
| Pin-to-Pin Propagation Delay | 7.5 ns | — |
| User Flash Memory | 8 Kbits | 4.0 Kbits |
| Core Voltage (VCCINT) | 1.8 V (1.71 V to 1.89 V) | — |
| I/O Voltage Support | 1.5 V, 1.8 V, 2.5 V, 3.3 V | — |
| Packhaging | 64-pin EQFP (exposed-pad QFP) | 64-pin EQFP (Exposed Pad) |
| Temperature na Operasyon | -40C to +125C (automotive AEC-Q100) | -40C to +100C (Industrial) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | — |
| Configuration Method | Non-volatile flash, instant-on | — |
| Tindminan RoHS | Compliant | Compliant |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Device Family | — | MAX V |
| Logic Elements (LEs) | — | 160 |
| Macrocells | — | 128 |
| Maximum User I/O Pins | — | 79 |
| Pin-to-Pin Logic Delay (tPD) | — | 7.5 ns |
| Logic Array Blocks (LABs) | — | 4 |
| Supply Voltage - Core | — | 3.3 V or 2.5 V |
| I/O Bank Voltages | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| JTAG Support | — | Yes (IEEE 1149.1, TMS/TDI/TDO/TCK) |
| Differential I/O | — | LVDS, RSDS, mini-LVDS, LVPECL (emulated) |
| Configuration | — | Non-volatile on-chip flash, instant-on |