5M160ZM100C5N vs 5M160ZE64I5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M160ZM100C5N sa pamamagitan ng Altera at 5M160ZE64I5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 5M160ZM100C5N | 5M160ZE64I5N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Device Family | MAX V | MAX V |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | — |
| Logic Elements | 160 | — |
| Maximum Internal Frequency | 184 MHz | — |
| Propagation Delay (tPD) | 7.9 ns | — |
| User I/Os | 79 | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Configuration Memory | Internal Flash (non-volatile) | — |
| Programming Interface | JTAG (IEEE 1532 / IEEE 1149.1) | — |
| Packhaging | 100-ball Micro FBGA (MBGA-100), 6 x 6 mm, 0.5 mm pitch | 64-pin EQFP (Exposed Pad) |
| Temperature na Operasyon | 0C to +85C (commercial) | -40C to +100C (Industrial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant | Compliant |
| Level ng MSL | 3 (168 hours) | — |
| Supported I/O Standards | LVCMOS, LVTTL, PCI (Bank 1 only via VCCIO) | — |
| Logic Elements (LEs) | — | 160 |
| Macrocells | — | 128 |
| Maximum User I/O Pins | — | 79 |
| Pin-to-Pin Logic Delay (tPD) | — | 7.5 ns |
| User Flash Memory | — | 4.0 Kbits |
| Logic Array Blocks (LABs) | — | 4 |
| Supply Voltage - Core | — | 3.3 V or 2.5 V |
| I/O Bank Voltages | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| JTAG Support | — | Yes (IEEE 1149.1, TMS/TDI/TDO/TCK) |
| Differential I/O | — | LVDS, RSDS, mini-LVDS, LVPECL (emulated) |
| Configuration | — | Non-volatile on-chip flash, instant-on |