5M160ZT100C5N vs 5M160ZT100C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M160ZT100C5N sa pamamagitan ng Altera at 5M160ZT100C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 5M160ZT100C5N | 5M160ZT100C4N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX V | — |
| Device Family | MAX V CPLD | — |
| Macro Cells | 128 | — |
| Logic Elements (LEs) | 160 | 160 |
| User I/Os | 79 | 79 |
| Number of Logic Array Blocks (LABs) | 8 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Operating Frequency | 152 MHz (typical, internal) | — |
| User Flash Memory (UFM) | 8 Kbits | 8 Kbits |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 1.5 V to 3.3 V | — |
| Temperature na Operasyon | 0 °C to +85 °C (commercial) | — |
| Packhaging | TQFP-100 | TQFP-100 (100-pin) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | 3 | 3 |
| Tindminan RoHS | Compliant | Compliant |
| Lead-Free | Yes | Yes |
| Programming Interface | JTAG (IEEE 1149.1) - in-system | — |
| Family | — | MAX V |
| Macrocells | — | 128 |
| Pin-to-Pin Logic Delay (tPD) | — | 7.9 ns |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Bank Supply (VCCIO) | — | 1.2 V to 3.3 V |
| Configuration Memory | — | Non-volatile flash |
| Programmability | — | In-system via JTAG (IEEE 1149.1) |
| Operating Temperature Grade | — | Commercial (0 C to +85 C) |
| Logic Array Blocks (LABs) | — | 2 |