5M240ZM100C5N vs 5M240ZM68C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M240ZM100C5N sa pamamagitan ng Intel at 5M240ZM68C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 5M240ZM100C5N | 5M240ZM68C5N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX V | MAX V (5M240Z) |
| Device | 5M240Z | — |
| Logic Elements (LEs) | 240 | — |
| Macrocells | 192 | — |
| User I/Os | 79 | — |
| Packhaging | 100-MBGA (FineLine BGA), 6 mm x 6 mm | 68-ball Micro FBGA (BGA-68) |
| Pin/Ball Count | 100 | — |
| Configuration Memory | On-chip flash, non-volatile | — |
| Core Voltage VCCINT | 1.71 V to 1.89 V (1.8 V nominal) | — |
| I/O Voltage VCCIO | 1.2 V to 3.3 V (MultiVolt, banked) | — |
| Pin-to-Pin Delay tPD | 7.5 ns | — |
| Register-to-Register tCO | 4.7 ns max | — |
| Temperature na Operasyon | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant | Compliant |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) |
| On-chip User Flash | Yes (8 Kbits) | — |
| Internal Oscillator | Yes | — |
| Series | — | MAX V |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Architecture | — | Non-volatile flash-based |
| Macro Cells | — | 192 |
| Logic Elements | — | 240 |
| Logic Array Blocks (LABs) | — | 4 |
| Maximum Operating Frequency | — | 118.3 MHz |
| Core Supply Voltage | — | 1.8 V (1.71 V to 1.89 V) |
| I/O Banks | — | MultiVolt I/O, 1.5/1.8/2.5/3.3 V compatible |
| Global Clocks | — | 4 |
| User Flash Memory | — | Yes (integrated) |