5M40ZE64C4N vs 5M160ZE64C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M40ZE64C4N sa pamamagitan ng Intel at 5M160ZE64C5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 5M40ZE64C4N | 5M160ZE64C5N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX V | — |
| Logic Elements (LE) | 32 | 160 |
| User Flash Memory | 4 Kbit | 8 Kbits |
| Pin-to-Pin Delay (tPD1) | 7.5 ns | — |
| Maximum Internal Frequency | 184 MHz | — |
| Number of I/O Pins | 30 (approx.) | — |
| Supply Voltage (VCCINT) | 1.8 V | 1.8 V |
| I/O Bank Voltage | 1.8 V / 2.5 V / 3.3 V | — |
| Process Technology | 0.18 µm flash-based CMOS | — |
| Configuration Memory | Non-volatile flash (internal) | Non-volatile Flash |
| Programmable Pull-up Resistors | Yes (per-pin, internal) | — |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) / In-system |
| Temperature na Operasyon | 0 °C to +85 °C (commercial) | 0°C to +85°C (commercial) |
| Packhaging | EQFP-64 (Plastic Enhanced QFP, 64 pins) | 64-pin EQFP (E64) with exposed pad |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | 3 (per JEDEC J-STD-020) | 3 |
| Tindminan RoHS | Compliant | Compliant |
| Series | — | MAX V |
| Device Family | — | MAX V (5M160Z) |
| Macrocells | — | 128 |
| User I/O Pins | — | 54 |
| Maximum Operating Frequency (fMAX) | — | 118.3 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 1.4 ns (per datasheet) |
| I/O Bank Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |