5M40ZE64I5N vs 5M40ZE64C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M40ZE64I5N sa pamamagitan ng Intel at 5M40ZE64C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 5M40ZE64I5N | 5M40ZE64C4N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Device Family | MAX V | — |
| Logic Elements (LE) | 40 | 32 |
| Macrocells | 32 | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count for 64-EQFP variant] | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency | [DATA_NEEDED: fMAX per datasheet] | 184 MHz |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Bank Voltage (VCCIO) | 1.2 V to 3.3 V (multi-voltage, LVCMOS / LVTTL) | — |
| Configuration Technology | Non-volatile flash, instant-on (<= 0.5 ms) | — |
| Standby Current | 25 µA (typical) | — |
| Temperature na Operasyon | -40 °C to +100 °C (Industrial, I-suffix) | 0 °C to +85 °C (commercial) |
| Packhaging | 64-pin EQFP (EQFP-64), 9 mm x 9 mm, 0.4 mm pitch | EQFP-64 (Plastic Enhanced QFP, 64 pins) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] | 3 (per JEDEC J-STD-020) |
| Lead-Free / RoHS | Lead free, plastic, RoHS compliant (per FindIC description) | — |
| JTAG Support | IEEE 1149.1 boundary-scan, in-system programmability | — |
| Toolchain | Quartus II (MAX V device support) / Quartus Prime | — |
| Family | — | MAX V |
| User Flash Memory | — | 4 Kbit |
| Pin-to-Pin Delay (tPD1) | — | 7.5 ns |
| Number of I/O Pins | — | 30 (approx.) |
| Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Bank Voltage | — | 1.8 V / 2.5 V / 3.3 V |
| Process Technology | — | 0.18 µm flash-based CMOS |
| Configuration Memory | — | Non-volatile flash (internal) |
| Programmable Pull-up Resistors | — | Yes (per-pin, internal) |
| Programming Interface | — | JTAG (IEEE 1149.1) |
| Tindminan RoHS | — | Compliant |