5M40ZM64C4N vs 5M40ZM64A5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M40ZM64C4N sa pamamagitan ng Altera at 5M40ZM64A5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 5M40ZM64C4N | 5M40ZM64A5N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX V | MAX V |
| Logic Elements | 40 | — |
| Macro Cells | 32 | — |
| Number of I/O Pins | 30 (max user I/O) | — |
| Number of Logic Array Blocks | 2 LABs (16 macrocells each) | — |
| Core Voltage VCCINT | 1.8 V (1.71 V to 1.89 V) | — |
| I/O Voltage VCCIO | 1.2 V to 3.3 V (multi-voltage) | — |
| Maximum Internal Frequency | 184.1 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 7.5 ns | — |
| Propagation Delay (max) | 7.5 ns | — |
| Temperature na Operasyon | 0 °C to +85 °C (commercial) | -40 °C to +125 °C (automotive) |
| Packhaging | 64-MBGA (Micro FineLine BGA), 4.5 x 4.5 mm | 64-pin EQFP (EQFP-64) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Configuration Memory | Flash (non-volatile, instant-on) | On-chip flash (non-volatile) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) + ISP |
| Tindminan RoHS | Compliant | Compliant |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Device Family Sub-series | — | 5M40Z |
| Logic Elements (LEs) | — | 32 |
| Macrocells | — | 32 |
| User I/Os | — | 30 |
| Logic Array Blocks (LABs) | — | 2 |
| Maximum Operating Frequency | — | 118.3 MHz |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) Standards | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V LVCMOS, LVTTL |
| Static Power Consumption | — | 25 µA typical |
| Process Technology | — | 0.18 µm flash CMOS |
| Internal Oscillator | — | Yes (on-chip) |
| Lead-Free | — | Yes |