5M570ZT100C4N vs 5M80ZT100C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M570ZT100C4N sa pamamagitan ng Intel at 5M80ZT100C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 5M570ZT100C4N | 5M80ZT100C4N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX V | MAX V |
| Device Logic Elements (Macrocells) | 440 | — |
| User I/Os | 74 | — |
| Packhaging | TQFP-100 (14x14 mm) | TQFP-100 (T100) |
| Bilang ng Pin | 100 | — |
| Configuration Memory | Internal flash (non-volatile) | — |
| User Flash Memory | 8 Kbits (typical, MAX V) | 8 Kbit |
| Core Supply Voltage | 1.8 V | — |
| I/O Supply Voltage (VCCIO) | 1.2 V to 3.3 V (bank-dependent) | — |
| Operating Temperature (Commercial) | 0 C to +85 C | — |
| Speed Grade | -4 | — |
| Programming Interface | JTAG (IEEE 1149.1) and in-system programmable | JTAG (IEEE 1149.1) |
| Typical Static Current | approx. 2 mA | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | 3 (168 hours) | — |
| Tindminan RoHS | Compliant | Compliant |
| Process Technology | 0.30 um 6-metal-layer flash CMOS | 0.18 µm flash CMOS |
| Logic Array Blocks (LABs) | Approx. 28 LABs (16 macrocells each) | — |
| Lead-Free / Halogen-Free | Yes | — |
| Logic Elements (LEs) | — | 80 |
| Macrocells | — | 64 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum User I/O Pins | — | 79 |
| Number of Global Clocks | — | 4 |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Temperature na Operasyon | — | 0C to +85C (Commercial) |
| Configuration Method | — | Non-volatile flash (instant-on) |