5M80ZE64C4N vs 5M160ZE64C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M80ZE64C4N sa pamamagitan ng Intel at 5M160ZE64C5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 5M80ZE64C4N | 5M160ZE64C5N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX V | — |
| Device Logic Elements | 64 | — |
| Number of Macro Cells | 64 | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| Maximum User I/O Pins | 79 | — |
| Maximum Operating Frequency | 184.1 MHz | — |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns] | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 1.5V / 1.8V / 2.5V / 3.3V | — |
| Programmability | In-system via JTAG (IEEE 1149.1) | — |
| Configuration Memory | Non-volatile flash, instant-on | Non-volatile Flash |
| Global Clocks | 2 | — |
| User Flash Memory | On-chip (8 Kbits) | 8 Kbits |
| Operating Temperature Grade | Commercial (0C to +85C) | — |
| Speed Grade | C4 | — |
| Packhaging | 64-pin EQFP (E64) with exposed pad | 64-pin EQFP (E64) with exposed pad |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL level] | 3 |
| Tindminan RoHS | Compliant (lead-free) | Compliant |
| Hot Socketing | Supported | — |
| Series | — | MAX V |
| Device Family | — | MAX V (5M160Z) |
| Logic Elements (LE) | — | 160 |
| Macrocells | — | 128 |
| User I/O Pins | — | 54 |
| Maximum Operating Frequency (fMAX) | — | 118.3 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 1.4 ns (per datasheet) |
| Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Bank Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Temperature na Operasyon | — | 0°C to +85°C (commercial) |
| Programming Interface | — | JTAG (IEEE 1149.1) / In-system |