5M80ZE64C4N vs 5M80ZM64C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M80ZE64C4N sa pamamagitan ng Intel at 5M80ZM64C4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 5M80ZE64C4N | 5M80ZM64C4N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX V | MAX V |
| Device Logic Elements | 64 | — |
| Number of Macro Cells | 64 | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| Maximum User I/O Pins | 79 | — |
| Maximum Operating Frequency | 184.1 MHz | 184.1 MHz |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns] | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 1.5V / 1.8V / 2.5V / 3.3V | — |
| Programmability | In-system via JTAG (IEEE 1149.1) | — |
| Configuration Memory | Non-volatile flash, instant-on | Non-volatile on-chip flash |
| Global Clocks | 2 | — |
| User Flash Memory | On-chip (8 Kbits) | 30 Kbit |
| Operating Temperature Grade | Commercial (0C to +85C) | — |
| Speed Grade | C4 | — |
| Packhaging | 64-pin EQFP (E64) with exposed pad | 64-ball MBGA (Micro FBGA), 4.5 mm × 4.5 mm, 0.5 mm pitch |
| Uri ng Pagpapasok | Surface Mount | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | Compliant (lead-free) | Compliant |
| Hot Socketing | Supported | — |
| Device | — | 5M80Z |
| Logic Elements (LE) | — | 64 |
| Macro Cells | — | 64 |
| Maximum User I/O | — | 79 |
| User SRAM | — | 8 Kbit |
| Pin-to-Pin Logic Delay (tPD1) | — | 7.5 ns |
| Core Supply Voltage | — | 1.8 V |
| Multi-Volt I/O Support | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| Operating Temperature (Commercial) | — | 0 °C to +85 °C |