74HC165D vs 74HC165D,652 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 74HC165D sa pamamagitan ng Nexperia at 74HC165D,652 sa pamamagitan ng Nexperia. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Nexperia
74HC165D,652 - 8-Bit Parallel-In/Serial-Out Shift Register | Nexperia
74HC165D,652 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 74HC165D | 74HC165D,652 |
|---|---|---|
| Brand | Nexperia | Nexperia |
| Kategorya | Logic ICs | Logic ICs |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Logic Type | Shift Register (Parallel-in / Serial-out, PISO) | Shift Register |
| Number of Elements | 1 | 1 |
| Bits per Element | 8 | — |
| Fungsi | 8-bit parallel-load / serial-in shift register with complementary serial outputs | Parallel or Serial to Serial |
| Supply Voltage (Vcc) | 2.0 V to 6.0 V | — |
| Input Type | Standard CMOS (HC); TTL-compatible variant is 74HCT165 | CMOS (HC); pin-compatible with TTL/LSTTL |
| Type ng Output | Complementary CMOS (Q7, Q7-bar) | Differential (complementary Q7 and Q7-bar) |
| Logic Family | 74HC / 74HCT (high-speed Si-gate CMOS, LSTTL pin-compatible) | 74HC (high-speed Si-gate CMOS) |
| Parallel Load | Asynchronous, active-low SH/LD | Asynchronous via SH/LD-bar |
| Serial Input | Synchronous DS on rising CLK edge | — |
| Temperature na Operasyon | -40 C to +125 C | -40 °C to +125 °C |
| Packhaging | 16-pin SOIC (SOT109-1) | 16-SOIC (SOT109-1), 0.154" (3.90 mm) width |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | 1 (unlimited) | — |
| Tindminan RoHS | Compliant | Compliant |
| JEDEC Compliance | JEDEC standard no. 7A | — |
| Number of Bits per Element | — | 8 |
| Supply Voltage (VCC) | — | 2 V to 6 V |
| Bilang ng Pins | — | 16 |
| Standard Compliance | — | JEDEC standard no. 7A |
| Pin Compatible With | — | Low-power Schottky TTL (LSTTL) |
| Serial Data Input | — | DS (for daisy-chaining) |
| Clock Input | — | CP (rising-edge triggered) with clock inhibit (CE-bar) |