A3P600-FG484 vs A3P600-1FGG484I Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng A3P600-FG484 sa pamamagitan ng Microchip Technology at A3P600-1FGG484I sa pamamagitan ng Microchip Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microchip Technology
A3P600-FG484 - ProASIC3 600K-Gate Flash FPGA, 484-BGA | Microchip
A3P600-FG484 ✓ NakahandaMicrochip Technology
A3P600-1FGG484I - 600K Gate Flash FPGA 235 I/O | Microchip
A3P600-1FGG484I ✓ NakahandaPagsanggunian na paghahambing
| Parametro | A3P600-FG484 | A3P600-1FGG484I |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | ProASIC3 (Flash FPGAs) | ProASIC3 |
| Total Gates | 600000 gates | — |
| Number of Registers | 13824 | — |
| VersaTiles (Logic Elements) | 13824 | — |
| Maximum User I/O | 235 I/O | — |
| System Performance | 231 MHz | Up to approx. 231 MHz (per Utmel family comparison) |
| Process Technology | 130 nm, 7-layer metal flash | — |
| Core Supply Voltage | 1.425 V to 1.575 V | — |
| Configuration Memory | On-chip flash (non-volatile, instant-on) | On-chip flash (nonvolatile, single chip) |
| Embedded Memory | Embedded block SRAM (18 kbit blocks) | — |
| Soft Processor Support | ARM Cortex-M1 (optional soft core) | — |
| Packhaging | 484-pin FBGA, 23x23 mm | 484-ball FBGA (FGG484) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +85C (TJ) | Industrial (-40C to +100C), I suffix |
| Tindminan RoHS | RoHS3 Compliant (lead-free per FGG variant) | — |
| Packaging | Tray | — |
| Programming | In-system programmable via JTAG, no external boot device | — |
| System Gates | — | 600000 |
| VersaTiles (D-flip-flops) | — | 13824 |
| User I/Os | — | 235 |
| Speed Grade | — | -1 |
| Core Voltage | — | 1.5 V |
| Technology | — | 130 nm flash process |
| Logic Architecture | — | VersaTile (LUT / D-flip-flop / latch) |
| I/O Banks | — | 4 (A3P600 per Microchip migration note) |
| Reprogrammability | — | Live reprogrammable (in-system) |
| Number of Dedicated RAM Blocks | — | [DATA_NEEDED: embedded memory blocks] |
| Max User Flash Memory | — | [DATA_NEEDED: embedded flash capacity] |
| DLL/PLL Resources | — | [DATA_NEEDED: clock conditioning resources] |