A42MX24-1PLG84I vs A42MX24-2PLG84I Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng A42MX24-1PLG84I sa pamamagitan ng Microchip Technology at A42MX24-2PLG84I sa pamamagitan ng Microchip Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microchip Technology
A42MX24-1PLG84I - 36K Gate MX FPGA, PLCC-84 | Microchip
A42MX24-1PLG84I ⚠ Huling PagbiliMicrochip Technology
A42MX24-2PLG84I - 36K Gate Antifuse FPGA, 84-PLCC | Microchip
A42MX24-2PLG84I ✓ NakahandaPagsanggunian na paghahambing
| Parametro | A42MX24-1PLG84I | A42MX24-2PLG84I |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| System Gates | 36000 | 36000 gates |
| Logic Cells / Logic Blocks | 912 | — |
| Family | MX (42MX) | MX (42MX) |
| Process Technology | 0.45 um CMOS | — |
| Volte ng Pagbibigay | 3V ~ 3.6V, 4.5V ~ 5.5V | — |
| I/O Count (this package) | 72 | — |
| Max User I/O (family) | 202 | — |
| Dual-Port SRAM | 2.5 kbits | — |
| Temperature na Operasyon | -40C to +85C | -40C to +85C (Industrial) |
| Packhaging | 84-LCC (J-Lead, PLCC-84) | 84-PLCC (J-Lead) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Logic Family | CMOS | — |
| Speed Grade | -1 | -2 |
| Tindminan RoHS | ROHS3 Compliant | Lead Free (per Kynix listing) |
| Packaging | Tray | Tray |
| Manufacturer Lead Time | 10 weeks | — |
| Product Status | Last Time Buy | — |
| Logic Cells | — | 912 cells |
| User I/O | — | 72 |
| Technology | — | 0.45 um antifuse |
| Core Architecture Voltage | — | 5.0 V |
| I/O Voltage Support | — | 3.3 V / 5.0 V mixed |
| Programmability | — | One-Time Programmable (antifuse) |
| Configuration | — | No external boot device required |
| Dedicated Decode Blocks | — | D-modules (wide-input AND, CPLD-like) |
| Primary Applications | — | ASIC alternative, legacy PLD integration |