AD9609BCPZ-80 vs AD9609XCPZ-40 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng AD9609BCPZ-80 sa pamamagitan ng Analog Devices at AD9609XCPZ-40 sa pamamagitan ng Analog Devices. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | AD9609BCPZ-80 | AD9609XCPZ-40 |
|---|---|---|
| Brand | Analog Devices | Analog Devices |
| Kategorya | ADC/DAC | ADC/DAC |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Number of Bits | 10 bit | — |
| Number of Channels | 1 | 1 |
| Architecture | Pipelined | Multi-stage differential pipeline |
| Rate ng Pagkupita | 80 MSPS | — |
| Sampling Rate (Family Options) | 20 / 40 / 65 / 80 MSPS (selected by part suffix) | — |
| Analog Supply Voltage | 1.8 V | — |
| Digital Output Supply | 3.3 V | — |
| Input Type | Single-ended / differential | Differential |
| Data Interface | Serial, SPI™ control port; parallel or 1-pair LVDS data output | — |
| On-chip Reference | Yes (1.0 V typical, external-reference option) | — |
| SNR (fIN = 9.7 MHz) | 61.5 dBFS | — |
| SNR (fIN = 200 MHz) | 61.0 dBFS | — |
| SFDR (fIN = 9.7 MHz) | 75 dBc | — |
| SFDR (fIN = 200 MHz) | 73 dBc | — |
| Hanay ng Temperature na Operasyon | -40 °C to +85 °C | -40 C to +85 C (industrial, per ADI product family) |
| Packhaging | 32-LFCSP-VQ (5x5 mm) with exposed pad | 32-LFCSP (5 mm x 5 mm) with exposed pad |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Power-Down Pin | SDIO/PDWN (CMOS-compatible) | — |
| Pin Compatibility | Pin-compatible with AD9629 (12-bit) and AD9649 (14-bit) families | — |
| Tindminan RoHS | Compliant | Compliant |
| Packaging (Shipping) | Tray | — |
| Pangangasiwaan | — | 10 bits |
| Sample Rate (Speed Grade) | — | 40 MSPS |
| Supply Voltage (Analog) | — | 1.8 V |
| Reference | — | Internal 1.0 V (external override option) |
| Sample-and-Hold Bandwidth | — | [DATA_NEEDED: full-power input bandwidth in MHz] |
| Digital Output Interface | — | CMOS, parallel |
| Output Coding | — | [DATA_NEEDED: binary or two's complement] |
| Power Dissipation | — | [DATA_NEEDED: power in mW at 40 MSPS] |
| Level ng MSL | — | 3 (per JEDEC J-STD-020, reflow at 260 C) |
| Family | — | AD9609 (20/40/65/80 MSPS speed grades) |