ADC1613D080HN-C18 vs ADC1112D125HN-C18 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng ADC1613D080HN-C18 sa pamamagitan ng Renesas Electronics at ADC1112D125HN-C18 sa pamamagitan ng Renesas Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Renesas Electronics
ADC1613D080HN-C18 - Dual 16-bit 80MSPS ADC w/ JESD204A | Renesas
ADC1613D080HN-C18 ✓ NakahandaRenesas Electronics
ADC1112D125HN-C18 - Dual 11-bit 125MSPS ADC, LVDS/CMOS | Renesas
ADC1112D125HN-C18 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | ADC1613D080HN-C18 | ADC1112D125HN-C18 |
|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics |
| Kategorya | ADC/DAC | ADC/DAC |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Pangangasiwaan | 16 bit | 11-bit |
| Number of Channels | 2 | 2 (dual, simultaneous sampling) |
| Architecture | Pipelined | — |
| Sample Rate (max per channel) | 80 MSPS | — |
| Family Sample Rate Variants | 65 / 80 / 105 / 125 MSPS | — |
| Data Interface | Serial JESD204A | — |
| Input Type | Differential analog inputs | Single-ended analog inputs (per channel) |
| Analog Supply Voltage | 3.0 V to 3.6 V | — |
| Digital Supply Voltage | 3.0 V to 3.6 V | — |
| Power Consumption (typ) | [DATA_NEEDED: typical power at 80 MSPS] | — |
| SFDR (typ) | [DATA_NEEDED: SFDR at 80 MSPS] | — |
| SNR (typ) | [DATA_NEEDED: SNR at 80 MSPS] | — |
| INL (max) | [DATA_NEEDED: integral non-linearity] | — |
| Packhaging | 56-HVQFN (8x8 mm) with exposed pad | HVQFN-64 (8x8 mm with exposed thermal pad) |
| Hanay ng Temperature na Operasyon | [DATA_NEEDED: industrial / extended grade] | -40 C to +85 C |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | 3 (per manufacturer handling guidelines) | 3 (168 hours) |
| Lead-Free / RoHS | Yes (per manufacturer datasheet) | — |
| Internal Reference | Yes | — |
| Sample Rate (Max) | — | 125 Msps |
| Analog Supply Voltage (AVDD) | — | 3.0 V to 3.6 V |
| Digital I/O Supply (OVDD) | — | 1.8 V to 3.3 V |
| Output Interface | — | CMOS or LVDS DDR (selectable) |
| Reference | — | Internal programmable (0-6 dB in 1 dB steps) or external |
| Control Interface | — | SPI (3-wire, mode configuration) |
| Power-Down Mode | — | Yes, per-channel via SPI |
| Tindminan RoHS | — | Compliant |