ADC34J44IRGZ25 vs ADS62P48IRGC25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng ADC34J44IRGZ25 sa pamamagitan ng Texas Instruments at ADS62P48IRGC25 sa pamamagitan ng Texas Instruments. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Texas Instruments
ADC34J44IRGZ25 - Quad 14-bit 125 MSPS ADC w/ JESD204B | Texas Instruments
ADC34J44IRGZ25 ✓ NakahandaTexas Instruments
ADS62P48IRGC25 - Dual 14-Bit 210MSPS ADC | Texas Instruments
ADS62P48IRGC25 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | ADC34J44IRGZ25 | ADS62P48IRGC25 |
|---|---|---|
| Brand | Texas Instruments | Texas Instruments |
| Kategorya | ADC/DAC | ADC/DAC |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Pangangasiwaan | 14 bit | 14 bit |
| Number of Channels | 4 | 2 (Dual) |
| Sample Rate | 125 MSPS | — |
| Architecture | Pipelined | Pipelined |
| Input Type | Differential | Differential analog inputs |
| Full-Scale Input Range | 1.0 Vpp | — |
| SNR (f_IN = 70 MHz) | 72 dBFS | — |
| SFDR (f_IN = 70 MHz) | 86 dBc | — |
| Channel-to-Channel Isolation | 105 dB | — |
| Power Consumption (per channel, 160 MSPS) | 203 mW | — |
| Digital Interface | JESD204B (Subclass 0/1/2) | — |
| Number of JESD204B Lanes | 1 per ADC (up to 160 MSPS) | — |
| Volte ng Pagbibigay | 1.8 V (single supply) | — |
| Internal Dither | Yes | Yes (programmable) |
| Multi-Chip Synchronization | Yes (SYSREF/SYNC~) | — |
| Hanay ng Temperature na Operasyon | -40C to +85C (Industrial) | -40 C to +85 C (Industrial) |
| Packhaging | 48-VQFN (7x7 mm, RGZ) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant | Compliant |
| Sample Rate (max) | — | 210 MSPS |
| Output Interface | — | DDR LVDS / Parallel CMOS (selectable) |
| Analog Supply Voltage | — | 1.8 V |
| Digital Supply Voltage | — | 3.3 V |
| Packhaging / Kaso | — | 64-VQFN (RGC) 9x9 mm (HVQCCN) |
| Bilang ng Pin | — | 64 |
| Level ng MSL | — | 3 |
| Lead Free | — | Yes |
| Input Clock Type | — | LVDS differential clock |
| Programmable Gain | — | Yes (improves SFDR at lower FS inputs) |