ATSAMA5D22A-CNR vs ATSAMA5D22B-CU Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng ATSAMA5D22A-CNR sa pamamagitan ng Microchip Technology at ATSAMA5D22B-CU sa pamamagitan ng Microchip Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microchip Technology
ATSAMA5D22A-CNR - 500MHz Cortex-A5 MPU, 196-TFBGA | Microchip
ATSAMA5D22A-CNR ✓ NakahandaMicrochip Technology
ATSAMA5D22B-CU - 500MHz ARM Cortex-A5 MPU, 196-TFBGA | Microchip
ATSAMA5D22B-CU ✓ NakahandaPagsanggunian na paghahambing
| Parametro | ATSAMA5D22A-CNR | ATSAMA5D22B-CU |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Kategorya | Microcontrollers | Microcontrollers |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Manufacturer | Microchip Technology | — |
| Series | SAMA5D2 | — |
| Core | ARM Cortex-A5 | — |
| Core Count | 1 | — |
| Width ng Data Bus | 32-bit | — |
| Maksimum na Taktiko ng Oras | 500 MHz | — |
| Packhaging | 196-TFBGA (11x11 mm), 0.75 mm pitch | 196-TFBGA (CSBGA), 11x11 mm, 0.8 mm pitch |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Supply Voltage - Core | 1.2 V | — |
| Supply Voltage - I/O | 1.8 V / 3.3 V | — |
| Temperature na Operasyon | -40C to +105C (Industrial, MRLA) | -40 C to +85 C (industrial) |
| External Memory Support | DDR2/DDR3/DDR3L/LPDDR1/LPDDR2/LPDDR3, QSPI, SD, eMMC | LPDDR1, LPDDR2, LPDDR3, DDR2, DDR3, DDR3L (16-bit) |
| On-chip SRAM | 128 KB | — |
| On-chip ROM | 160 KB | — |
| Cryptography | AES, SHA, TRNG, Secure Boot | — |
| Ethernet | 10/100 Mbps + 10/100/1000 Mbps MAC | — |
| USB | 3x USB 2.0 + HSIC | — |
| CAN | 3x CAN-FD | — |
| Display Controller | TFT LCD up to 1024x768 | — |
| ADC | 12-bit | — |
| Tindminan RoHS | ROHS3 Compliant | Compliant |
| Core Processor | — | ARM Cortex-A5 (32-bit, single core) |
| Core Architecture | — | ARMv7-A with TrustZone and NEON |
| Maximum CPU Clock | — | 500 MHz |
| L1 Instruction Cache | — | 32 Kbytes |
| L1 Data Cache | — | 32 Kbytes |
| L2 Cache / SRAM | — | 128 Kbytes (configurable as internal SRAM) |
| Memory Architecture | — | MMU (full virtual memory support) |
| Flash Interfaces | — | 2x QSPI, e.MMC |
| Supply Voltage (core) | — | 1.2 V (typ, internal regulator) |
| Supply Voltage (I/O) | — | 3.3 V (typ) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Lead-Free / Halogen-Free | — | Lead-free finish; halogen status [DATA_NEEDED] |