ATSAMA5D26A-CUR vs ATSAMA5D26A-CU Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng ATSAMA5D26A-CUR sa pamamagitan ng Microchip Technology at ATSAMA5D26A-CU sa pamamagitan ng Microchip Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microchip Technology
ATSAMA5D26A-CUR - 500MHz Cortex-A5 MPU, 289-LFBGA | Microchip
ATSAMA5D26A-CUR ✓ NakahandaMicrochip Technology
ATSAMA5D26A-CU - Cortex-A5 MPU 500MHz | 289-LFBGA | Microchip
ATSAMA5D26A-CU ✓ NakahandaPagsanggunian na paghahambing
| Parametro | ATSAMA5D26A-CUR | ATSAMA5D26A-CU |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Kategorya | Microcontrollers | Microcontrollers |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Core Architecture | ARM Cortex-A5 (ARMv7-A) | — |
| Maximum CPU Clock | 500 MHz | 500 MHz |
| Core Count | 1 | — |
| Bit Width | 32-bit | — |
| Internal SRAM | 128 KB | 128 KB |
| Internal ROM | 160 KB | — |
| L1 Instruction Cache | 32 KB | — |
| L1 Data Cache | 32 KB | — |
| FPU / NEON | Yes (single-precision FPU + NEON) | — |
| Memory Interfaces | DDR2, DDR3L, LPDDR2, LPDDR3, QSPI, e.MMC, NAND, NOR | — |
| External Memory Bus | 16-bit EBI | DDR2/DDR3L/LPDDR2/LPDDR3, 16-bit |
| Display Controller | Integrated LCD controller up to WXGA (1366x768) | LCD with resistive/capacitive touchscreen I/F |
| Ethernet | 2x 10/100 Mbps EMAC (GMII/RGMII/MII) | 10/100 Mbps MAC (GMII/RMII/MII) |
| USB | 2x USB 2.0 High-Speed Host + 1x USB 2.0 Device/Host | — |
| CAN | 2x CAN-FD | 2x CAN-FD |
| Crypto Accelerator | AES, SHA, TRNG, secure boot | — |
| ADC | 12-bit, 1 Msps, up to 12 channels | — |
| Packhaging | 289-LFBGA, 14x14 mm, 0.8 mm pitch | 289-LFBGA, 14x14 mm, 0.8 mm pitch |
| Supply Voltage (Core) | 1.2 V (typ) | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL rating] |
| Tindminan RoHS | Compliant | Compliant |
| Core | — | Arm Cortex-A5 (single-core) |
| Architecture | — | ARMv7-A |
| Boot Memory | — | QSPI, e.MMC, NAND Flash |
| I/O Voltage Rails | — | 1.2 V, 1.8 V, 3.3 V |
| USB Ports | — | 3x USB 2.0 (1 HSIC, 2 host/device) |
| Cryptography | — | AES, SHA-256, TRNG, secure boot |