CD4017BEE4 vs CD4017BE Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng CD4017BEE4 sa pamamagitan ng Texas Instruments at CD4017BE sa pamamagitan ng Texas Instruments. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Texas Instruments
CD4017BEE4 - CMOS Decade Counter/Divider, 10MHz, 16-PDIP | TI
CD4017BEE4 ✓ NakahandaTexas Instruments
CD4017BE - CMOS Decade Counter/Divider, 16-PDIP | Texas Instruments
CD4017BE ✓ NakahandaPagsanggunian na paghahambing
| Parametro | CD4017BEE4 | CD4017BE |
|---|---|---|
| Brand | Texas Instruments | Texas Instruments |
| Kategorya | Logic ICs | Logic ICs |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Logic Family | CD4000 (CMOS) | CMOS 4000B series |
| Counter Type | Decade Counter / Divider | — |
| Number of Elements | 1 | 1 |
| Number of Bits per Element | 10 | 10 |
| Trigger Type | Positive, Negative Edge | Positive edge |
| Supply Voltage (VDD) | 3 V to 18 V | 3 V to 18 V |
| Typical Clock Frequency @ VDD=10V | 10 MHz (typ) | — |
| Quiescent Current Test | 100% tested at 20 V | — |
| Parametric Ratings | 5 V, 10 V, 15 V | — |
| Output Kumpigurasyon | Decoded 1-of-10 active-high | — |
| Carry Output | Active-low carry-out (CO) | — |
| Master Reset | Yes (active-high) | Yes (active-high) |
| Clock Inhibit | Yes | — |
| Temperature na Operasyon | -55 C to +125 C | -55C to +125C |
| Packhaging / Kaso | 16-DIP (0.300 inch, 7.62 mm) | — |
| Uri ng Pagpapasok | Through Hole | Through-hole |
| Standard | JEDEC Tentative Standard No. 13-A | — |
| Tindminan RoHS | Compliant | Compliant (TI product) |
| Fungsi | — | Counter, Decade (divide-by-10) with 10 decoded outputs |
| Count Direction | — | Up |
| Typical Clock Frequency | — | 10 MHz (typ) at VDD = 10 V |
| Kuru-kuryente ng Kapayapaan | — | 100% tested at 20 V (per datasheet) |
| Number of Decoded Outputs | — | 10 (Q0 through Q9) |
| Carry Out (CO) Signal | — | Yes - for cascading |
| Clock Enable | — | Yes (active-low enable) |
| Packhaging | — | 16-Pin PDIP (N) |
| JEDEC Standard | — | Meets JEDEC Tentative Standard No. 13A (per datasheet reference) |