EP1810GM883B vs EP1810GC-35AB Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GM883B sa pamamagitan ng Altera at EP1810GC-35AB sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810GM883B | EP1810GC-35AB |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Device Family | EP1810 (Classic EPLD) | — |
| Macrocells | 48 | — |
| User Flip-Flops | Up to 64 | — |
| Total Inputs | 60 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 (bidirectional, tri-state) | — |
| Propagation Delay (tPD) | 50 ns max | 35 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | 5 V |
| Technology | CMOS, UV-erasable | CMOS EPROM |
| Temperature na Operasyon | -55 °C to +125 °C (Military, MIL-STD-883B) | [DATA_NEEDED: operating temperature range] |
| Package Type | Ceramic Pin Grid Array (PGA), 84 pins | Pin Grid Array (PGA), ceramic |
| Package Designator | GM (ceramic PGA) | — |
| Processing Level | MIL-STD-883B (Class B) | — |
| Programming Method | UV-erasable / Altera programming hardware | UV-erasable EPROM, in-system via JTAG-like interface |
| Uri ng Pagpapasok | Through-hole (PGA socket or PCB through-hole) | — |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Family | TTL-compatible I/O | — |
| Product Family | — | Classic EPLD |
| Number of Macrocells | — | 48 |
| Number of Usable Gates | — | 1200 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Number of I/O Pins | — | 48 |
| Dedicated Input Pins | — | 12 |
| Maximum Toggle Frequency | — | 62.5 MHz |
| Tindminan RoHS | — | unknown |