EP1810LC-20T vs EP1810GI-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-20T sa pamamagitan ng Intel at EP1810GI-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810LC-20T | EP1810GI-45 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 900 gates | — |
| Macrocells | 48 | 24 |
| Logic Array Blocks (LABs) | 4 x 12 macrocells | — |
| Maximum Toggle Frequency | 50 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 20 ns | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | PLCC-68 (J-lead) | Ceramic Pin Grid Array with UV window |
| Uri ng Pagpapasok | Surface Mount (socket-compatible) | Through-Hole |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE 1149.1) and Altera Master/Slave serial | — |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Shipping Format | Tape & Reel ("T" suffix) | — |
| Tindminan RoHS | Non-compliant (legacy 5V PLCC) | Non-compliant (ceramic PGA) |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Flip-Flops | — | 48 |
| Propagation Delay (tpd) | — | 45 ns |
| Speed Grade | — | -45 |
| Technology | — | CMOS |
| Bilang ng Pin | — | 68 |
| Programmable | — | Yes (UV-erasable, electrically programmable) |
| Lead-Free | — | No |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCC range] |