EP1810LC-35T vs EP1810LC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-35T sa pamamagitan ng Intel at EP1810LC-35 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP1810LC-35T | EP1810LC-35 |
|---|---|---|
| Brand | Intel | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Device Family | EP1810 Classic EPLD | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Usable Gates | 900 | — |
| Macro Cells | 48 | — |
| Pin-to-Pin Delay (tpd) | 35 ns | — |
| Maximum Frequency (fmax) | 28.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS | CMOS, UV-erasable EPROM |
| Logic Compatibility | 100% TTL emulation | — |
| Packhaging | 68-pin PLCC (Plastic Leaded Chip Carrier) | 68-pin PLCC (J-Lead) |
| Package Suffix | T = Tape and Reel | — |
| Temperature na Operasyon | 0 C to +70 C (Commercial) | 0C to +70C (commercial) |
| Uri ng Pagpapasok | Surface Mount (PLCC socket or direct solder) | Surface Mount (socketable) |
| Programming Method | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II | — |
| Tindminan RoHS | Non-compliant (legacy PLCC product) | [DATA_NEEDED] |
| Logic Family Replacement Target | 74LS low-power Schottky TTL | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Series | — | Classic EP1810 |
| Macrocells | — | 48 |
| Equivalent Gates | — | 900 usable / 2100 equivalent |
| Maximum Operating Frequency | — | 28.6 MHz |
| Propagation Delay (tpd) | — | 35 ns (max, '-35' speed grade) |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| I/O Pins | — | [DATA_NEEDED: I/O count exact] |
| Configuration Method | — | UV-erase + EPROM programmer |
| Programmable Interconnect | — | Centralized Programmable Interconnect Array (PIA) |
| Development Tool (legacy) | — | MAX+PLUS II / A+PLUS |
| Lead-Free | — | [DATA_NEEDED] |