EP1810LC-45 vs EP1810LI-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-45 sa pamamagitan ng Rochester Electronics at EP1810LI-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810LC-45 EP1810LI-25
Brand Rochester Electronics Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Altera Classic EPLD Altera Classic EPLD
Device Type EPLD (Erasable Programmable Logic Device) EPLD (Erasable Programmable Logic Device), UV-erasable / OTP
Usable Gates 900 900
Macro Cells 48 —
Maximum Inputs 64 —
Maximum Outputs 48 —
Logic Array Blocks 4 —
Propagation Delay (tpd) 45 ns —
Maximum Operating Frequency 22.2 MHz —
Supply Voltage (Vcc) 5 V (±5%) —
Process Technology 5 V CMOS EPROM CMOS
Packhaging 68-pin PLCC (J-lead) 68-pin PLCC (J68, J-Lead)
Temperature na Operasyon 0 °C to +70 °C (commercial) —
Uri ng Pagpapasok Surface Mount (PLCC socket compatible) —
Tindminan RoHS [DATA_NEEDED: RoHS status of Rochester-sourced part] unknown
Lead-Free [DATA_NEEDED: lead-free finish] —
Macrocells — 48
Propagation Delay (tPD) — 25 ns
Maximum Counter Frequency — 40 MHz
Supply Voltage (VCC) — 4.5 V to 5.5 V (nominal 5 V)
I/O Pins — 48
Dedicated Inputs — 12
Global Clock Inputs — 4
Interconnect — Programmable global and local buses
JESD-30 Package Code — S-PQCC-J68
Operating Temperature (Industrial 'I' suffix) — -40 C to +85 C
Programming Mode — EPROM/UV-erasable (windowed) and OTP
Development Tool — Altera MAX+PLUS II
Lead-Free Status — unknown

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