EP1AGX50CF484I6N vs EP1AGX60CF484I7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1AGX50CF484I6N sa pamamagitan ng Intel at EP1AGX60CF484I7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Intel
EP1AGX50CF484I6N EP1AGX50CF484I6N - 3.125 Gbps, 50K FPGA | Altera

EP1AGX50CF484I6N - 3.125 Gbps, 50K FPGA | Altera

EP1AGX50CF484I6N Obsolete

Pagsanggunian na paghahambing

Parametro EP1AGX50CF484I6N EP1AGX60CF484I7N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Device Type Field Programmable Gate Array (FPGA) —
Series Arria GX —
Programmable Logic Capacity 2,475,072 bits —
Number of Configurable Logic Blocks 50,160 —
Number of LABs 2,508 —
Number of User I/O 229 —
Maximum Serial Transceiver Data Rate 3.125 Gbps —
Packhaging 484-BBGA, FCBGA 484-ball FineLine BGA (1.0 mm pitch)
Terminal Count 484 —
Package Body Width 23 mm —
Package Body Length 23 mm —
Terminal Pitch 1 mm —
Terminal Form Ball —
Temperature Grade Industrial —
Lead-Free Yes —
Core Clock 640 MHz —
Configuration Status Not Verified —
Product Status Obsolete —
Uri ng Pagpapasok Surface Mount —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status from Altera/Intel product page]
REACH Status [DATA_NEEDED: REACH status] —
Hanay ng Temperature na Operasyon [DATA_NEEDED: operating temperature range] —
Family — Arria GX
Logic Elements — 60,100
Embedded Memory — 2,528,640 bits
Embedded 18x18 Multipliers — 240 (estimated from family datasheet, [DATA_NEEDED: exact count])
Maximum User I/O Pins — 229
Transceiver Channels — Up to 12 high-speed SERDES channels
Transceiver Data Rate — Up to 3.125 Gbps
PLLs — 4
Global Clocks — [DATA_NEEDED: global clock count]
Operating Temperature (Industrial) — -40C to +100C (I7 grade)
Core Voltage — 1.2 V typical
I/O Standards Supported — LVDS, LVPECL, SSTL, HSTL, PCI, PCI-X, LVTTL, LVCMOS
Configuration Modes — Passive Serial, JTAG, Fast Passive Parallel
Level ng MSL — 3 (per JEDEC J-STD-020, typical for FineLine BGA)

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