EP1AGX50DF1152I5N vs EP1AGX50DF1152I4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1AGX50DF1152I5N sa pamamagitan ng Altera at EP1AGX50DF1152I4N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1AGX50DF1152I5N | EP1AGX50DF1152I4N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Arria GX | Arria GX |
| Logic Elements | 50160 | — |
| Logic Array Blocks (LABs) | 2508 | — |
| Embedded Memory | 2475072 bits (approximately 2420 Kbit) | 2475072 bits |
| Total Memory Bits | 2475072 | — |
| Number of I/O | 514 | — |
| Number of Transceivers | [DATA_NEEDED: number of transceiver channels] | — |
| Transceiver Data Rate | 3.125 Gbps | — |
| Supply Voltage Core | 1.2 V | — |
| Packhaging | 1152-BBGA (FineLine BGA, flip-chip) | 1152-ball FineLine BGA |
| Package Code | F1152 | — |
| Temperature na Operasyon | -40C to +100C (Industrial) | -40C to +100C (Industrial) |
| Temperature Grade | I (Industrial) | — |
| Speed Grade | 5 | I4 |
| Configuration Method | SRAM, JTAG, Passive Serial, Fast Passive Parallel | Passive serial / Fast passive parallel / JTAG |
| Tindminan RoHS | Compliant (lead-free) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Logic Elements (LE) | — | 50160 |
| User I/O Pins | — | 514 |
| Maximum User I/O Banks | — | [DATA_NEEDED: number of IO banks] |
| Transceivers | — | Up to 3.125 Gbps multi-gigabit transceivers |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Lead-Free / RoHS | — | Yes (RoHS Compliant) |
| Process Node | — | [DATA_NEEDED: process technology] |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| PLL Count | — | [DATA_NEEDED: PLL count] |