EP1C12F324C7N vs EP1C20F324C6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1C12F324C7N sa pamamagitan ng Intel at EP1C20F324C6 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1C12F324C7N | EP1C20F324C6 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Series | Cyclone | — |
| Family | Cyclone I | Cyclone |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements (LEs) | 12,060 | — |
| Logic Array Blocks (LABs) | 1,206 | — |
| Embedded Memory (bits) | 239,616 | — |
| Maximum User I/O | 249 | — |
| Number of PLLs | 2 | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Core Voltage | 1.5 V | — |
| Supply Voltage na Operasyon | 1.5 V to 3.3 V | — |
| Maximum Internal Frequency | 320 MHz | 405.2 MHz |
| Speed Grade | C7 (commercial, -40C to 85C; spec datasheet: 0C to 85C) | 6 |
| Packhaging / Kaso | 324-BGA (FBGA-324, 19 x 19 mm, 1.0 mm pitch) | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Configuration Method | AS / PS / JTAG | — |
| Tindminan RoHS | Compliant (N suffix = lead-free) | — |
| Temperature na Operasyon | [DATA_NEEDED: precise commercial temperature range per datasheet] | — |
| Logic Elements (LE) | — | 20,060 |
| Embedded RAM Bits | — | 294,912 bits (64 M4K blocks × 4,608 bits) |
| User I/O Count | — | 233 |
| Core Voltage (VCCINT) | — | 1.5 V |
| I/O Voltage Standards | — | LVCMOS / LVTTL (3.3 V, 2.5 V, 1.8 V, 1.5 V), LVDS |
| PLLs | — | 4 |
| LVDS Data Rate (per pair) | — | Up to 640 Mbps |
| Memory Interfaces | — | DDR SDRAM, QDR SRAM, SDR SDRAM |
| Packhaging | — | 324-ball FBGA (FineLine BGA) |
| Temperature Grade | — | Commercial (0 °C to +85 °C) |
| Configuration Modes | — | Active Serial (AS), Passive Serial (PS), JTAG |