EP1C4F400C6N vs EP1C4F400I7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1C4F400C6N sa pamamagitan ng Intel at EP1C4F400I7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1C4F400C6N | EP1C4F400I7 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Manufacturer | Intel (formerly Altera) | — |
| Series | Cyclone (Cyclone I) | Cyclone |
| Logic Elements (LEs) | 4,000 | — |
| Total RAM Bits | 78,336 | 78336 |
| Embedded RAM Blocks | M4K (4 Kbits each) | — |
| User I/Os | 301 | — |
| PLL | 2 PLLs | — |
| Package Type | 400-ball FineLine BGA | — |
| Package Code (JEDEC) | F400 / FBGA-400 | — |
| Process Technology | 0.13 µm SRAM CMOS | CMOS 130 nm |
| Configuration Method | SRAM (serial EPCS or JTAG) | — |
| Speed Grade | C6 (commercial) | -7 |
| Operating Temperature (commercial C grade) | 0 °C to +85 °C | — |
| Supply Voltage VCCINT | 1.5 V | — |
| Supply Voltage VCCIO | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | — |
| MSL (Moisture Sensitivity) | MSL3 | — |
| Tindminan RoHS | Compliant (per Altera/Intel product page) | [DATA_NEEDED: RoHS status for EP1C4F400I7] |
| Lead-Free | Yes | — |
| Product Type | — | FPGA - Field Programmable Gate Array |
| Number of Logic Cells / Elements | — | 4000 |
| Number of LABs | — | 400 |
| Number of User I/Os | — | 301 |
| Core Supply Voltage | — | 1.5 V |
| Maximum Internal Frequency | — | 320 MHz (family level) |
| Packhaging / Kaso | — | 400-BGA (FBGA/PBGA), 21 x 21 mm, 1.0 mm pitch |
| Number of Terminals | — | 400 |
| Style ng Pagpapasok | — | Surface Mount (BGA) |
| Temperature Grade | — | Industrial (I7 suffix) |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: exact industrial temperature range] |
| Number of PLLs | — | [DATA_NEEDED: PLL count] |