EP1C6T144I7N vs EP1C6T14417N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1C6T144I7N sa pamamagitan ng Intel at EP1C6T14417N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1C6T144I7N | EP1C6T14417N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | Cyclone | — |
| Family | Cyclone (1st generation) | Cyclone |
| Logic Elements | 5,980 | 5,980 |
| Logic Array Blocks (LABs) | 598 | — |
| Total RAM Bits | 92,160 | 92,160 |
| Embedded RAM Blocks | 20 x M4K (4 Kbit each) | — |
| PLLs | 2 | 2 |
| User I/O Pins | 98 | — |
| I/O Banks | 4 | — |
| Core Voltage | 1.5 V | — |
| I/O Voltage | 1.5 V to 3.3 V | — |
| Maximum LVDS Pairs | 64 | — |
| Packhaging | 144-LQFP (TQFP-144) | TQFP-144 (1.0 mm pitch) |
| Temperature na Operasyon | -40 °C to +100 °C | 0C to +85C (commercial) |
| Speed Grade | I7 (industrial, slowest) | 7 (-7) |
| Uri ng Pagpapasok | Surface Mount | — |
| Process Technology | 0.13 μm SRAM | 130 nm TSMC |
| Configuration Modes | AS, PS, JTAG | — |
| Tindminan RoHS | Compliant | Compliant |
| Level ng MSL | 3 (168 hours) | — |
| Embedded M4K RAM Blocks | — | 20 |
| Maximum User I/O Pins | — | 185 |
| Global Clock Networks | — | 20 |
| LVDS Channels | — | 34 differential pairs (max) |
| Core Voltage (VCCINT) | — | 1.5 V (typical) |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) |
| Configuration Mode | — | Active Serial (AS) / Passive Serial (PS) / JTAG |