EP1K100FI256-2N vs EP1K100FC256-2N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1K100FI256-2N sa pamamagitan ng Intel at EP1K100FC256-2N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1K100FI256-2N | EP1K100FC256-2N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | ACEX 1K | ACEX 1K |
| Series | EP1K100 | — |
| Logic Elements | 4,992 | — |
| System Gates | 100,000 | — |
| Logic Array Blocks (LABs) | 624 | — |
| Embedded Array Blocks (EABs) | 6 | — |
| Total RAM Bits | 49,152 | — |
| Maximum User I/O | 186 | — |
| Process Technology | 0.22 µm CMOS | — |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Speed Grade | -2 (faster bin) | — |
| Ball Finish | Leaded (SnPb) - 'N' suffix | — |
| Temperature na Operasyon | -40 °C to +85 °C (Industrial) | — |
| Packhaging | 256-ball FineLine BGA (FBGA-256) | 256-pin FBGA |
| Uri ng Pagpapasok | Surface Mount | — |
| Configuration Interface | JTAG (IEEE 1149.1) + serial modes | — |
| Tindminan RoHS | Non-compliant (leaded 'N' ball finish) | unknown |
| Product Type | — | Field Programmable Gate Array (FPGA) |
| Logic Capacity | — | 100K gates |
| Logic Cells | — | 4992 cells |
| RAM Capacity | — | 49152 bits |
| Logic Array Blocks | — | 624 LABs |
| User I/O Count | — | 186 I/Os |
| Maximum Frequency | — | 250 MHz |
| Technology | — | 0.22 µm CMOS |
| Core Voltage | — | 2.5 V |
| Loadable PLD Delay | — | 0.5 ns |
| Package Type | — | Fine-pitch ball grid array |
| Terminal Count | — | 256 terminals |
| Temperature Grade | — | Commercial |
| Katayuan ng Lifecycle | — | Obsolete |
| REACH Status | — | unknown |
| AEC-Q100 | — | not_qualified |